Datasheet

 2009-2012 Microchip Technology Inc. DS80490L-page 11
PIC16(L)F1933
11. Module: BOR
11.1 BOR Reset
This issue affects only the PIC16LF1933 device.
The device may undergo a BOR Reset when
waking-up from Sleep and BOR is re-enabled. A
BOR Reset may also occur the moment the
software BOR is enabled.
Under certain voltage and temperature conditions
and when either SBODEN or BOR_NSLEEP is
selected, the devices may occasionally reset when
waking-up from Sleep or BOR is enabled.
Work around
Method 1: In applications where BOR use is
not critical, turn off the BOR in the
Configuration Word.
Method 2: Set the FVREN bit of the
FVRCON register. Maintain this
bit on at all times.
Method 3: When BOR module is needed
only during run-time, use the
software-enabled BOR by setting
the SBODEN option on the
Configuration Word. BOR should
be turned off by software before
Sleep, then follow the below
sequence for turning BOR on
after wake-up:
a. Wake-up event occurs;
b. Turn on FVR (FVREN bit of the
FVRCON register);
c. Wait until FVRRDY bit is set;
d. Wait 15 µs after the FVR
Ready bit is set;
e. Manually turn on the BOR.
Method 4: Use the software-enabled BOR
as described in Method 3, but use
the following sequence:
a. Switch to internal 32 kHz
oscillator immediately before
Sleep;
b. Upon wake-up, turn on FVR
(FVREN bit of the FVRCON
register);
c. Manually turn on the BOR;
d. Switch the clock back to the
preferred clock source.
Affected Silicon Revisions
12. Module: Oscillator
12.1 Oscillator Start-up Timer (OST) bit
During the Two-Speed Start-up sequence, the
OST is enabled to count 1024 clock cycles. After
the count is reached, the OSTS bit is set, the
system clock is held low until the next falling edge
of the external crystal (LP, XT or HS mode), before
switching to the external clock source.
When an external oscillator is configured as the
primary clock and Fail-Safe Clock mode is enabled
(FCMEN = 1), any of the following conditions will
result in the Oscillator Start-up Timer (OST) failing
to restart:
•MCLR
Reset
• Wake from Sleep
• Clock change from INTOSC to Primary Clock
This anomaly will manifest itself as a clock failure
condition for external oscillators which take longer
than the clock failure time-out period to start.
Work around
None.
Affected Silicon Revisions
Note: When using the software BOR follow the
steps in Methods 3 or 4 above when
enabling BOR for the first time during
program execution.
A1 A2 A3 A4 A6 A7 A8
X X XX
A1 A2 A3 A4 A6 A7 A8
X X XXX X X