Datasheet

2011-2013 Microchip Technology Inc. DS40001453E-page 5
PIC16(L)F1847
PIN ALLOCATION TABLE
TABLE 1: 18/20/28-PIN SUMMARY (PIC16(L)F1847)
I/O
18-Pin PDIP/SOIC
20-Pin SSOP
28-Pin QFN/UQFN
ANSEL
ADC
Reference
Cap Sense
Comparator
SR Latch
Timers
CCP
EUSART
MSSP
Interrupt
Modulator
Pull-up
Basic
RA0 17 19 23 Y AN0 CPS0 C12IN0- SDO2 N
RA1 18 20 24 Y AN1 CPS1 C12IN1- SS2 N
RA2 1 1 26 Y AN2 VREF-
DACOUT
CPS2 C12IN2-
C12IN+
N
RA3 2 2 27 Y AN3 VREF+ CPS3 C12IN3-
C1IN+
C1OUT
SRQ CCP3 N
RA4 3 3 28 Y AN4 CPS4 C2OUT SRNQ T0CKI CCP4 N
RA5 4 4 1 N SS1
(1)
Y
(2)
MCLR
VPP
RA6 15 17 20 N P1D
(1)
P2B
(1)
SDO1
(1)
N OSC2
CLKOUT
CLKR
RA7 16 18 21 N P1C
(1)
CCP2
(1)
P2A
(1)
N OSC1
CLKIN
RB0 6 7 7 N SRI T1G CCP1
(1)
P1A
(1)
FLT0
INT
IOC
Y
RB1 7 8 8 Y AN11 CPS11 RX
(1,3)
DT
(1,3)
SDA1
SDI1
IOC Y
RB2 8 9 9 Y AN10 CPS10 RX
(1)
DT
(1)
TX
(1,3)
CK
(1,3)
SDA2
SDI2
SDO1
(1,3)
IOC MDMIN Y
RB3 9 10 10 Y AN9 CPS9 CCP1
(1,3)
P1A
(1,3)
IOC MDOUT Y
RB4 10 11 12 Y AN8 CPS8 SCL1
SCK1
IOC MDCIN2 Y
RB5 11 12 13 Y AN7 CPS7 P1B TX
(1)
CK
(1)
SCL2
SCK2
SS1
(1,3)
IOC Y
RB6 12 13 15 Y AN5 CPS5 T1CKI
T1OSCI
P1C
(1,3)
CCP2
(1,3)
P2A
(1,3)
IOC Y ICSPCLK
RB7 13 14 16 Y AN6 CPS6 T1OSCO P1D
(1,3)
P2B
(1,3)
IOC MDCIN1 Y ICSPDAT
VDD 14 15,
16
17,
19
VDD
Vss 5 5,6 3,5 ——VSS
Note 1: Pin functions can be moved using the APFCON register(s).
2: Weak pull-up always enabled when MCLR
is enabled, otherwise the pull-up is under user control.
3: Default function location.