Datasheet

PIC16(L)F1847
DS40001453E-page 312  2011-2013 Microchip Technology Inc.
FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL 118
APFCON1
— — — — — — —
TXCKSEL 118
BAUDCON
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298
INTCON GIE PEIE
TMR0IE INTE IOCE TMR0IF INTF IOCF 88
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 89
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 93
RCREG EUSART Receive Data Register 292*
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 297
SPBRGL BRG<7:0> 299*
SPBRGH BRG<15:8> 299*
TRISB TRISB7 TRISB6
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 126
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 296
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
* Page provides register information.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)