Datasheet

 2011-2013 Microchip Technology Inc. DS40001453E-page 27
PIC16(L)F1847
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bank 0
000h
(1)
INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
001h
(1)
INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
002h
(1)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
003h
(1)
STATUS — — —TOPD ZDCC---1 1000 ---q quuu
004h
(1)
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
005h
(1)
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
006h
(1)
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
007h
(1)
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
008h
(1)
BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000
009h
(1)
WREG Working Register 0000 0000 uuuu uuuu
00Ah
(1)
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
00Bh
(1)
INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000u
00Ch PORTA
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx
00Dh PORTB
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx
00Eh
— Unimplemented — —
00Fh
— Unimplemented — —
010h
— Unimplemented — —
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF
— — CCP2IF 0000 0--0 0000 0--0
013h PIR3
— — CCP4IF CCP3IF TMR6IF — TMR4IF — --00 0-0- --00 0-0-
014h PIR4
— — — — — — BCL2IF SSP2IF ---- --00 ---- --00
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
—TMR1ON0000 00-0 uuuu uu-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111
01Ch T2CON
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
01Dh
— Unimplemented — —
01Eh CPSCON0 CPSON CPSRM
— — CPSRNG<1:0> CPSOUT T0XCS 00-- 0000 00-- 0000
01Fh CPSCON1
— — — — CPSCH<3:0> ---- 0000 ---- 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: Unimplemented, read as ‘1’.