Datasheet

 2011-2013 Microchip Technology Inc. DS40001453E-page 267
PIC16(L)F1847
25.6.6 I
2
C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDAx pin after the falling edge of SCLx is
asserted. SCLx is held low for one Baud Rate Genera-
tor rollover count (T
BRG). Data should be valid before
SCLx is released high. When the SCLx pin is released
high, it is held that way for TBRG. The data on the SDAx
pin must remain stable for that duration and some hold
time after the next falling edge of SCLx. After the 8th bit
is shifted out (the falling edge of the 8th clock), the BF
flag is cleared and the master releases SDAx. This
allows the slave device being addressed to respond
with an ACK
bit during the 9th bit time if an address
match occurred, or if data was received properly. The
status of ACK is written into the ACKSTAT bit on the ris-
ing edge of the 9th clock. If the master receives an
Acknowledge, the Acknowledge Status bit, ACKSTAT,
is cleared. If not, the bit is set. After the 9th clock, the
SSPxIF bit is set and the master clock (Baud Rate Gen-
erator) is suspended until the next data byte is loaded
into the SSPxBUF, leaving SCLx low and SDAx
unchanged (Figure 25-28).
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCLx until all
seven address bits and the R/W
bit are completed. On
the falling edge of the 8th clock, the master will release
the SDAx pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the 9th clock, the
master will sample the SDAx pin to see if the address
was recognized by a slave. The status of the ACK
bit is
loaded into the ACKSTAT Status bit of the SSPxCON2
register. Following the falling edge of the 9th clock
transmission of the address, the SSPxIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPxBUF takes place,
holding SCLx low and allowing SDAx to float.
25.6.6.1 BF Status Flag
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all eight bits are shifted out.
25.6.6.2 WCOL Status Flag
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
25.6.6.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPxCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK
= 0) and is set when the slave does not
Acknowledge (ACK
= 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
25.6.6.4 Typical Transmit Sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
2. SSPxIF is set by hardware on completion of the
Start.
3. SSPxIF is cleared by software.
4. The MSSPx module will wait the required start
time before any other operation takes place.
5. The user loads the SSPxBUF with the slave
address to transmit.
6. Address is shifted out the SDAx pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
7. The MSSPx module shifts in the ACK
bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
8. The MSSPx module generates an interrupt at
the end of the 9th clock cycle by setting the
SSPxIF bit.
9. The user loads the SSPxBUF with eight bits of
data.
10. Data is shifted out the SDAx pin until all eight
bits are transmitted.
11. The MSSPx module shifts in the ACK
bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the SSPx-
CON2 register. Interrupt is generated once the
Stop/Restart condition is complete.