Datasheet

 2011-2013 Microchip Technology Inc. DS40001453E-page 241
PIC16(L)F1847
25.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL
118
ANSELA
— — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0
122
ANSELB
ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 —
127
INTCON GIE PEIE
TMR0IE INTE IOCE TMR0IF INTF IOCF
88
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
89
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
93
SSP1BUF
Synchronous Serial Port Receive Buffer/Transmit Register
235*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0>
283
SSP1CON3
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
285
SSP1STAT SMP CKE
D/A P S R/W UA BF 281
SSP2BUF Synchronous Serial Port Receive Buffer/Transmit Register
235*
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
283
SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
285
SSP2STAT
SMP CKE D/A
PSR/WUA BF
281
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
120
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 126
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
* Page provides register information.