PIC16(L)F1847 18/20/28-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU: • C Compiler Optimized Architecture • 256 bytes Data EEPROM • Up to 14 Kbytes Linear Program Memory Addressing • Up to 1024 bytes Linear Data Memory Addressing • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset • Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data me
PIC16(L)F1847 Peripheral Highlights (Continued): • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications Note: XLP PIC12(L)F1822 (1) 2K 256 128 6 4 4 1 2/1 1 1 0/1/0 Y PIC12(L)F1840 (2) 4K 256 256 6 4 4 1 2/1 1 1 0/1/0 Y PIC16(L)F1823 (1) 2K 256 128 12 8 8 2 2/1 1 1 1/0/0 Y PIC16(L)F1824 (3) 4K 256 256 12 8 8 2 4/1 1 1 1/1/2 Y PIC16(L)F1825 (4) 8K 256 1024 12 8 8 2 4/1 1 1 1/1/2 Y PIC16(L)F1826 (5) 2K 256 256 16 12 12 2 2/1 1 1 1/0/0 Y PIC16(L)F1827 (5) 4K 256 384 16 12 12 2 4/1
PIC16(L)F1847 PIN DIAGRAMS Pin Diagram – 18-Pin PDIP, SOIC 1 18 RA3 RA4 2 17 RA1 RA0 16 RA7 RA5/MCLR/VPP 3 4 15 RA6 14 VDD 13 RB7/ICSPDAT 12 RB6/ICSPCLK PIC16(L)F1847 RA2 VSS 5 RB0 6 RB1 RB2 7 8 11 RB5 RB3 9 10 RB4 Note: See Table 1 for location of all peripheral functions.
PIC16(L)F1847 2: DS40001453E-page 4 RA1 RA0 NC 24 23 22 15 RB6/ICSPCLK RB5 NC RB4 18 NC 17 VDD 16 RB7/ICSPDAT 14 RA2 NC 25 PIC16(L)F1847 RB1 Note 1: 21 RA7 20 RA6 19 VDD 11 12 13 NC RB0 RA3 5 6 7 RB3 NC 4 RA4 NC VSS 28 2 3 8 9 10 1 NC VSS RB2 RA5/ MCLR/VPP 27 26 Pin Diagram – 28-Pin QFN/UQFN See Table 1 for location of all peripheral functions. It is recommended that the exposed bottom pad be connected to VSS. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 PIN ALLOCATION TABLE 18-Pin PDIP/SOIC 20-Pin SSOP 28-Pin QFN/UQFN ANSEL ADC Reference Cap Sense Comparator SR Latch Timers CCP EUSART MSSP Interrupt Modulator Pull-up Basic 18/20/28-PIN SUMMARY (PIC16(L)F1847) I/O TABLE 1: RA0 17 19 23 Y AN0 — CPS0 C12IN0- — — — — SDO2 — — N — RA1 18 20 24 Y AN1 — CPS1 C12IN1- — — — — SS2 — — N — RA2 1 1 26 Y AN2 VREFDACOUT CPS2 C12IN2C12IN+ — — — — — — — N — RA3 2 2 27 Y AN3 VREF
PIC16(L)F1847 TABLE OF CONTENTS 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15 3.0 Memory Organization ................................................................................
PIC16(L)F1847 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC16(L)F1847 NOTES: DS40001453E-page 8 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 1.0 DEVICE OVERVIEW The PIC16(L)F1847 are described within this data sheet. They are available in 18/20/28-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1847 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC16(L)F1847 FIGURE 1-1: PIC16(L)F1847 BLOCK DIAGRAM Program Flash Memory CLKR RAM EEPROM Clock Reference Timing OSC2/CLKOUT Generation OSC1/CLKIN PORTA CPU INTRC Oscillator (Figure 2-1) PORTB MCLR SR Latch ADC 10-Bit Timer0 Timer1 Timer2 Timer4 Timer6 DAC Comparators ECCP1 ECCP2 CCP3 CCP4 MSSP1 MSSP2 Modulator EUSART FVR CapSense Note 1: 2: DS40001453E-page 10 See applicable chapters for more information on peripherals.
PIC16(L)F1847 TABLE 1-2: PIC16(L)F1847 PINOUT DESCRIPTION Name RA0/AN0/CPS0/C12IN0-/SDO2 RA1/AN1/CPS1/C12IN1-/SS2 RA2/AN2/CPS2/C12IN2-/ C12IN+/VREF-/DACOUT RA3/AN3/CPS3/C12IN3-/C1IN+/ VREF+/C1OUT/CCP3/SRQ RA4/AN4/CPS4/C2OUT/T0CKI/C CP4/SRNQ RA5/MCLR/VPP/SS1 Function Input Type Output Type RA0 TTL AN0 AN — ADC Channel 0 input. CPS0 AN — Capacitive sensing input 0. C12IN0- AN — Comparator C1 or C2 negative input. SDO2 — RA1 TTL AN1 AN — ADC Channel 1 input.
PIC16(L)F1847 TABLE 1-2: PIC16(L)F1847 PINOUT DESCRIPTION (CONTINUED) Name RA6/OSC2/CLKOUT/CLKR/ P1D(1)/P2B(1)/SDO1(1) RA7/OSC1/CLKIN/P1C(1)/ CCP2(1)/P2A(1) RB0/T1G/CCP1(1)/P1A(1)/INT/ SRI/FLT0 RB1/AN11/CPS11/RX(1,2)/DT(1,2)/ SDA1/SDI1 RB2/AN10/CPS10/MDMIN/ TX(1,2)/CK(1,2)/RX(1)/DT(1)/ SDA2/SDI2/SDO1(1,2) Function Input Type RA6 TTL OSC2 — Output Type Description CMOS General purpose I/O. XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output.
PIC16(L)F1847 TABLE 1-2: PIC16(L)F1847 PINOUT DESCRIPTION (CONTINUED) Name RB3/AN9/CPS9/MDOUT/ CCP1(1,2)/P1A(1,2) RB4/AN8/CPS8/SCL1/SCK1/ MDCIN2 RB5/AN7/CPS7/P1B/TX(1)/CK(1)/ SCL2/SCK2/SS1(1,2) RB6/AN5/CPS5/T1CKI/T1OSI/ P1C(1,2)/CCP2(1,2)/P2A(1,2)/ ICSPCLK RB7/AN6/CPS6/T1OSO/ P1D(1,2)/P2B(1,2)/MDCIN1/ ICSPDAT Function Input Type RB3 TTL Output Type Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN9 AN — ADC Channel 9 input.
PIC16(L)F1847 NOTES: DS40001453E-page 14 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC16(L)F1847 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator S
PIC16(L)F1847 3.0 MEMORY ORGANIZATION There are three types of memory in PIC16(L)F1847: Data Memory, Program Memory and Data EEPROM Memory(1). • Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM - Device Memory Maps - Special Function Registers Summary • Data EEPROM memory(1) The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.
PIC16(L)F1847 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1847 PC<14:0> CALL, RETURN RETFIE, RETLW Reset Vector 0000h Interrupt Vector 0004h 0005h07FFh 0800h0FFFh 1000h 17FFh 1800h 1FFFh 2000h Page 2 Page 3 Rollover Page 0 (1) Rollover Page 3(1) Note 1: 3.1.1 The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
PIC16(L)F1847 3.2 Data Memory Organization 3.2.1.1 STATUS Register The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): The STATUS register, shown in Register 3-1, contains: • • • • The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled.
PIC16(L)F1847 3.
PIC16(L)F1847 3.3.1 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.3.2 GENERAL PURPOSE RAM There are up to 80 bytes of GPR in each data memory bank. 3.3.2.
2011-2013 Microchip Technology Inc.
PIC16(L)F1847 MEMORY MAP, BANKS 8-15 BANK 8 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — TMR4 PR4 T4CON — — — — TMR6 PR6 T6CON — BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h
2011-2013 Microchip Technology Inc.
PIC16(L)F1847 MEMORY MAP, BANKS 24-31 BANK 24 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 TABLE 3-7: PIC16(L)F1847 MEMORY MAP, BANK 31 Bank 31 FA0h Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH = Unimplemented data memory locations, read as ‘0’. DS40001453E-page 26 3.3.
PIC16(L)F1847 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 000h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h(1) PCL Program Counter (PC) Least Signif
PIC16(L)F1847 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 1 080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 082h(1) PCL Program Counter (PC)
PIC16(L)F1847 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 102h(1) PCL Program Counter (PC)
PIC16(L)F1847 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 182h(1) PCL Program Counter (PC)
PIC16(L)F1847 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 202h(1) PCL Program Counter (PC)
PIC16(L)F1847 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 5 280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 282h(1) PCL Program Counter (PC)
PIC16(L)F1847 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 6 300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 302h(1) PCL Program Counter (PC)
PIC16(L)F1847 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 382h(1) PCL Program Counter (PC)
PIC16(L)F1847 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 8 400h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 401h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 402h(1) PCL Program Counter (PC)
PIC16(L)F1847 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Banks 9-30 x00h/ x80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(1) PCL
PIC16(L)F1847 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 31 F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(1) PCL Program Counter (PC
PIC16(L)F1847 3.4 PCL and PCLATH 3.4.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC.
PIC16(L)F1847 3.5 Stack 3.5.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow.
PIC16(L)F1847 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC16(L)F1847 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.5.
PIC16(L)F1847 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001453E-page 42 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0x1FFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC16(L)F1847 3.6.2 3.6.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC16(L)F1847 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and programmers.
PIC16(L)F1847 4.
PIC16(L)F1847 REGISTER 4-1: bit 2-0 Note 1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.
PIC16(L)F1847 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 LVP DEBUG — BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 U-1 R-1 U-1 U-1 — — — Reserved — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltag
PIC16(L)F1847 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words.
PIC16(L)F1847 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.
PIC16(L)F1847 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC16(L)F1847 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Oscillator Timer1 FOSC<2:0> = 100 T1OSO T1OSCEN Enable Oscillator IRCF<3:0> HFPLL 500 kHz Source 16 MHz (HFINTOSC) Postscaler Internal Oscillator Block 500 kHz (MFINTOSC) 31 kHz Source 31 kHz 31 kHz (LFINTOSC) DS40001453E-page 52 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.
PIC16(L)F1847 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained internally within the oscillator module.
PIC16(L)F1847 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep RP(3) OSC2/CLKOUT Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
PIC16(L)F1847 5.2.1.5 5.2.1.6 TIMER1 Oscillator External RC Mode The Timer1 Oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required.
PIC16(L)F1847 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 “Clock Switching”for more information.
PIC16(L)F1847 5.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number.
PIC16(L)F1847 5.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4X PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: • The FOSC bits in Configuration Words must be set to use the INTOSC source as the device system clock (FOSC<2:0> = 100).
PIC16(L)F1847 FIGURE 5-7: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC
PIC16(L)F1847 5.3 Clock Switching 5.3.3 TIMER1 OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins.
PIC16(L)F1847 5.4 Two-Speed Clock Start-up Mode 5.4.1 Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC16(L)F1847 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
PIC16(L)F1847 5.5 Fail-Safe Clock Monitor 5.5.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC).
PIC16(L)F1847 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS40001453E-page 64 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 5.
PIC16(L)F1847 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator i
PIC16(L)F1847 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = • • • 000001 = 000000
PIC16(L)F1847 NOTES: DS40001453E-page 68 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 6.0 REFERENCE CLOCK MODULE 6.3 Conflicts with the CLKR pin The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR) and provide a secondary internal clock source to the modulator module. This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application.
PIC16(L)F1847 6.
PIC16(L)F1847 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Name CLKRCON Legend: Bit 7 Bit 6 Bit 5 CLKREN CLKROE CLKRSLR CONFIG1 Legend: Bit 3 CLKRDC<1:0> Bit 2 Bit 1 Bit 0 CLKRDIV<2:0> Register on Page 70 — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.
PIC16(L)F1847 NOTES: DS40001453E-page 72 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 7.0 RESETS There are multiple ways to reset this device: • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 7-1.
PIC16(L)F1847 7.1 Power-on Reset (POR) 7.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16(L)F1847 FIGURE 7-2: BROWN-OUT READY SBOREN TBORRDY BORRDY FIGURE 7-3: BOR Protection Active BROWN-OUT SITUATIONS VDD Internal Reset VBOR TPWRT(1) VDD Internal Reset VBOR < TPWRT TPWRT(1) VDD Internal Reset Note 1: VBOR TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 7.
PIC16(L)F1847 7.4 MCLR 7.8 The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 7-2). TABLE 7-2: MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 7.4.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up.
PIC16(L)F1847 FIGURE 7-4: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC DS40001453E-page 78 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 7.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 7-3 and Table 7-4 show the Reset conditions of these registers.
PIC16(L)F1847 7.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUNF) MCLR Reset (RMCLR) The PCON register bits are shown in Register 7-2. 7.
PIC16(L)F1847 TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN — — — — — — BORRDY 76 PCON STKOVF STKUNF — — RMCLR RI POR BOR 80 STATUS — — — TO PD Z DC C 20 WDTCON — — SWDTEN 101 WDTPS<4:0> Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
PIC16(L)F1847 NOTES: DS40001453E-page 82 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce Interrupts. Refer to the corresponding chapters for details.
PIC16(L)F1847 8.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register) 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins.
PIC16(L)F1847 FIGURE 8-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(00
PIC16(L)F1847 FIGURE 8-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Dummy Cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1).
PIC16(L)F1847 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F1847 8.
PIC16(L)F1847 REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gat
PIC16(L)F1847 REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0
PIC16(L)F1847 REGISTER 8-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 — — CCP4IE CCP3IE TMR6IE — TMR4IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 CCP4IE: CCP4 Interrupt Enable bit 1 = Enables the CCP4 interru
PIC16(L)F1847 REGISTER 8-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — BCL2IE SSP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit 1 = Enables the MSSP2 Bus Colli
PIC16(L)F1847 REGISTER 8-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = In
PIC16(L)F1847 REGISTER 8-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not
PIC16(L)F1847 REGISTER 8-8: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 — — CCP4IF CCP3IF TMR6IF — TMR4IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 CCP4IF: CCP4 Interrupt Flag bit 1 = Interrupt is pending 0 =
PIC16(L)F1847 REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 — — — — — — BCL2IF SSP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware bit 7-2 Unimplemented: Read as ‘0’ bit 1 BCL2IF: MSSP2 Bus Collision Interrupt Flag b
PIC16(L)F1847 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. WDT will be cleared but keeps running, if enabled for operation during Sleep. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5.
PIC16(L)F1847 9.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared.
PIC1(L)F1847 10.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC1(L)F1847 10.1 Independent Clock Source 10.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. 10.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 10-1. 10.2.1 WDT IS ALWAYS ON When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on. WDT protection is active during Sleep. 10.2.
PIC1(L)F1847 10.
PIC1(L)F1847 NOTES: DS40001453E-page 102 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 11.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs).
PIC16(L)F1847 11.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 30.
PIC16(L)F1847 Required Sequence EXAMPLE 11-2: DATA EEPROM WRITE BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BTFSC GOTO INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, $-2 ;Disable INTs.
PIC16(L)F1847 11.3 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash Program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software.
PIC16(L)F1847 EXAMPLE 11-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF BCF BSF NOP NOP BSF EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; ; Do not se
PIC16(L)F1847 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH:EEADRL register pair with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD, FREE and WREN bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the erase operation.
PIC16(L)F1847 After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will FIGURE 11-2: continue to run. The processor does not stall when LWLO = 1, loading the write latches.
PIC16(L)F1847 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY - Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2.
PIC16(L)F1847 EXAMPLE 11-5: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL 4.
PIC16(L)F1847 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. 8. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16(L)F1847 11.6 Write/Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 11-6) to the desired value to be written. Example 11-6 shows how to verify a write to EEPROM.
PIC16(L)F1847 11.
PIC16(L)F1847 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select
PIC16(L)F1847 REGISTER 11-6: W-0/0 EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit
PIC16(L)F1847 12.0 I/O PORTS 12.1 Depending on the device selected and peripherals enabled, there are two ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC16(L)F1847 12.
PIC16(L)F1847 12.3 PORTA Registers 12.3.1 DATA REGISTER PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-4). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC16(L)F1847 12.
PIC16(L)F1847 REGISTER 12-5: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 — LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 LATA<7:6>: RA<7:6> Output Latch Value bits(1) bit 5 Unimplemented: Read as ‘0’ bit 4-0
PIC16(L)F1847 REGISTER 12-7: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 ANSA<4:0>: Analog Select between Analog or Digital Function on
PIC16(L)F1847 12.4.1 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 12-1. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC, comparator and CapSense inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers.
PIC16(L)F1847 TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 122 LATA7 LATA6 — LATA4 LATA3 LATA2 LATA1 LATA0 121 WPUEN INTEDG TMR0CS TMR0SE PSA PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 120 WPUA — — WPUA5 — — — — — 121 Bit 8/0 Register on Page Name ANSELA LATA OPTION_REG Legend:
PIC16(L)F1847 12.5 PORTB and TRISB Registers 12.5.1 DATA REGISTER PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-9). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1847 12.
PIC16(L)F1847 REGISTER 12-11: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-u
PIC16(L)F1847 12.6.1 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 12-4. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.
PIC16(L)F1847 13.0 INTERRUPT-ON-CHANGE The PORTB pins can be configured to operate as Interrupt-on-change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin can be configured to generate an interrupt.
PIC16(L)F1847 REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bi
PIC16(L)F1847 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 127 INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 88 Name IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 130 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 130 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP
PIC16(L)F1847 NOTES: DS40001453E-page 132 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 14.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with a nominal output level (VFVR) of 1.024V. The output of the FVR can be configured to supply a reference voltage to the following: • ADC input channel • Comparator positive input • Comparator negative input The FVR can be enabled by setting the FVREN bit of the FVRCON register. 14.
PIC16(L)F1847 14.
PIC16(L)F1847 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between of -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16(L)F1847 NOTES: DS40001453E-page 136 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 16.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal.
PIC16(L)F1847 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.
PIC16(L)F1847 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 125 ns (2) (2) (2) (2) Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) Fosc/16 101 800 ns 800 ns 1.0 s Fosc/32 1.0 s 010 200 ns 1.6 s 250 ns 2.0 s Fosc/64 110 2.0 s 3.2 s 4.0 s FRC x11 1.
PIC16(L)F1847 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC16(L)F1847 16.2 16.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 “ADC Conversion Procedure”.
PIC16(L)F1847 16.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F1847 16.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC16(L)F1847 REGISTER 16-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 R/W-0/0 — ADNREF R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified.
PIC16(L)F1847 REGISTER 16-3: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-4: R/W-x/u A
PIC16(L)F1847 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC16(L)F1847 16.3 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4.
PIC16(L)F1847 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC16(L)F1847 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — ADNREF CHS<4:0> ADCS<2:0> Bit 1 Bit 0 Register on Page GO/DONE ADON 143 ADPREF<1:0> 144 ADRESH ADC Result Register High 145, 146 ADRESL ADC Result Register Low 145, 146 ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 122 ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 127 — — GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF PIE1
PIC16(L)F1847 NOTES: DS40001453E-page 150 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 17.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels.
PIC16(L)F1847 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD VREF+ R R 2 R DACEN DACLPS R R 32 Steps R 32-to-1 MUX DACPSS<1:0> DACR<4:0> 5 DAC (To Comparator and ADC Modules) R DACOUT R DACOE DACNSS VREF- VSOURCE- VSS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS40001453E-page 152 DACOUT + – Buffered DAC Output 2011-2013 Microchip Technology In
PIC16(L)F1847 17.4 Low Power Voltage State In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSOURCE+), or the negative voltage source, (VSOURCE-) can be disabled. The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source. 17.4.
PIC16(L)F1847 17.
PIC16(L)F1847 TABLE 17-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Bit 7 Bit 6 Bit 5 Bit 4 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> DACCON1 — — — Legend: Bit 3 Bit 2 DACR<4:0> Bit 1 Bit 0 ADFVR<1:0> — DACNSS Register on page 134 154 154 — = unimplemented, read as ‘0’. Shaded cells are unused with the DAC module. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 NOTES: DS40001453E-page 156 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 18.0 SR LATCH The module consists of a single SR latch with multiple Set and Reset inputs as well as separate latch outputs. The SR latch module includes the following features: • • • • Programmable input selection SR latch output is available externally Separate Q and Q outputs Firmware Set and Reset The SR latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications. 18.
PIC16(L)F1847 FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRPS Pulse Gen(2) SRLEN SRQEN SRI S SRSPE SRCLK Q SRQ SRSCKE sync_C2OUT(3) SRSC2E sync_C1OUT(3) SRSC1E SRPR SR Latch(1) Pulse Gen(2) SRI SRRPE SRCLK SRRCKE sync_C2OUT(3) SRRC2E R Q SRNQ SRLEN SRNQEN sync_C1OUT(3) SRRC1E Note 1: 2: 3: DS40001453E-page 158 If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 Pulse generator causes a 1 Q-state pulse width. Name denotes the connection point at the comparator output.
PIC16(L)F1847 TABLE 18-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 110 256 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz 101 100 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz 011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz 010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz 001 8 4 MHz 2.
PIC16(L)F1847 REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SR latch is set when the SR
PIC16(L)F1847 TABLE 18-2: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 122 SRPS SRCON0 SRLEN SRQEN SRNQEN SRCON1 SRSPE SRSCKE SRCLK<2:0> SRSC2E SRSC1E SRRPE SRRCKE SRRC2E TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 SRPR 159 SRRC1E 160 TRISA0 120 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module.
PIC16(L)F1847 NOTES: DS40001453E-page 162 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 19.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC16(L)F1847 FIGURE 19-2: CxNCH<1:0> COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM CxON(1) 2 CxINTP Interrupt det C12IN0- 0 C12IN1C12IN2- 1 MUX 2 (2) C12IN3- 3 Set CxIF det CXPOL CxVN D Cx(3) CxVP C1IN+ DAC 0 MUX 1 (2) FVR Buffer2 2 C12IN+ 3 CxHYS CxSP async_CxOUT To ECCP PWM Logic CXSYNC 0 CXOE TRIS bit CXOUT 2 D 1: 2: 3: To Data Bus EN Q1 (from Timer1) T1CLK Note CXOUT MCXOUT Q + CxON CXPCH<1:0> CxINTN Interrupt Q 1 To Timer1 or SR Latch sync_CXOUT When CxON = 0, t
PIC16(L)F1847 FIGURE 19-3: COMPARATOR 2 MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<1:0> CxON(1) 2 CxINTP Interrupt det C12IN0- 0 C12IN1- 1 MUX 2 (2) C12IN2C12IN3- 3 Set CxIF det CXPOL CxVN D Cx(3) CxVP C12IN+ DAC 0 MUX 1 (2) CxINTN Interrupt CXOUT MCXOUT Q To Data Bus + EN Q1 CxHYS CxSP To ECCP PWM Logic async_CxOUT 2 FVR Buffer2 3 CXSYNC CxON VSS CXPCH<1:0> 0 CXOE TRIS bit CXOUT 2 D (from Timer1) T1CLK Note 1: 2: 3: Q 1 To Timer1 or SR Latch sync_CxOUT When CxON = 0, the
PIC16(L)F1847 19.2 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1.
PIC16(L)F1847 19.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. See Section 30.
PIC16(L)F1847 19.7 Comparator Negative Input Selection The CxNCH<1:0> bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input. Note: 19.8 To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
PIC16(L)F1847 FIGURE 19-4: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS VA = Analog Voltage = Threshold Voltage VT Note 1: See Section 30.0 “Electrical Specifications”. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and
PIC16(L)F1847 REGISTER 19-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 U-0 — — R/W-0/0 R/W-0/0 CxNCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag
PIC16(L)F1847 TABLE 19-2: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 122 C1OE C1POL — C1SP C1HYS C1SYNC — — — C2SP — — — CM1CON0 C1ON C1OUT CM1CON1 C1NTP C1INTN CM2CON0 C2ON C2OUT CM2CON1 C2NTP C2INTN CMOUT DACCON0 DACCON1 FVRCON INTCON C1PCH<1:0> C2OE C2POL C2PCH<1:0> — — — — — DACEN DACLPS DACOE — DACPSS<1:0> TSRNG CDAFVR<1:
PIC16(L)F1847 20.0 TIMER0 MODULE 20.1.2 In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal.
PIC16(L)F1847 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16(L)F1847 REGISTER 20-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
PIC16(L)F1847 NOTES: DS40001453E-page 176 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 21.0 TIMER1 MODULE WITH GATE CONTROL • • • • The Timer1 module is a 16-bit timer/counter with the following features: Figure 21-1 is a block diagram of the Timer1 module.
PIC16(L)F1847 21.1 Timer1 Operation 21.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 21-2 displays the clock source selections. 21.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle.
PIC16(L)F1847 21.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 21.4 Timer1 Oscillator A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output).
PIC16(L)F1847 21.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 Gate circuitry. 21.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 Gate circuitry. 21.6.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1 Gate Control.
PIC16(L)F1847 21.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 21.
PIC16(L)F1847 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 N DS40001453E-page 182 N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF DS40001453E-page 184 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL N+4 Cleared by software 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 21.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 21-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC16(L)F1847 21.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 21-2, is used to control Timer1 Gate.
PIC16(L)F1847 TABLE 21-5: Name ANSELB CCP1CON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 127 P1M<1:0> DC1B<1:0> CCP1M<3:0> 226 GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 89 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 93 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 126 INTCON PORTB TMR1
PIC16(L)F1847 NOTES: DS40001453E-page 188 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 22.0 TIMER2/4/6 MODULES There are up to three identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). Note: The ‘x’ variable used in this section is used to designate Timer2, Timer4, or Timer6. For example, TxCON references T2CON, T4CON or T6CON. PRx references PR2, PR4 or PR6.
PIC16(L)F1847 22.1 Timer2/4/6 Operation The clock input to the Timer2/4/6 modules is the system instruction clock (FOSC/4). TMRx increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS<1:0> of the TxCON register. The value of TMRx is compared to that of the Period register, PRx, on each clock cycle.
PIC16(L)F1847 REGISTER 22-1: U-0 TXCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 TOUTPS<3:0> R/W-0/0 R/W-0/0 TMRxON bit 7 R/W-0/0 TxCKPS<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer Output Postscaler Select bits 0000 = 1:
PIC16(L)F1847 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Register on Page Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 88 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 89 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 93 PIE3 — — CCP4IE CCP3IE TMR6IE — TMR4IE — 91 PIR3 — — CCP4IF CCP3IF TMR6IF — TMR4IF — 95 PR2 Timer2 Module Period Register 189* PR4 T
PIC16(L)F1847 23.0 DATA SIGNAL MODULATOR Using this method, the DSM can generate the following types of Key Modulation schemes: The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output.
PIC16(L)F1847 23.1 DSM Operation The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register, disables the DSM module by automatically switching the carrier high and carrier low signals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current.
PIC16(L)F1847 FIGURE 23-2: ON OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 EXAMPLE 23-1: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State FIGURE 23-3: CARH CARL CARH CARL CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Car
PIC16(L)F1847 FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State FIGURE 23-5: CARH CARL CARH CARL FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State DS40001453E-page 196 CARH CARL CARH CARL 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 23.5 Carrier Source Polarity Select The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL register. 23.6 Carrier Source Pin Disable Some peripherals assert control over their corresponding output pin when they are enabled.
PIC16(L)F1847 REGISTER 23-1: MDCON: MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R-0/0 U-0 U-0 R/W-0/0 MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modu
PIC16(L)F1847 REGISTER 23-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-x/u U-0 U-0 U-0 MDMSODIS — — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDMS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDMSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by
PIC16(L)F1847 REGISTER 23-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 MDCHODIS MDCHPOL MDCHSYNC — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the p
PIC16(L)F1847 REGISTER 23-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 MDCLODIS MDCLPOL MDCLSYNC — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the per
PIC16(L)F1847 NOTES: DS40001453E-page 202 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 24.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
PIC16(L)F1847 24.1 Capture Mode 24.1.2 The Capture mode function described in this section is available and identical for CCP modules ECCP1, ECCP2, CCP3 and CCP4. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively.
PIC16(L)F1847 24.1.5 CAPTURE DURING SLEEP 24.1.6 Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state.
PIC16(L)F1847 24.2 Compare Mode 24.2.2 The Compare mode function described in this section is available and identical for CCP modules ECCP1, ECCP2, CCP3 and CCP4. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair.
PIC16(L)F1847 24.2.5 COMPARE DURING SLEEP 24.2.6 The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. TABLE 24-4: Name ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1.
PIC16(L)F1847 24.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
PIC16(L)F1847 24.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCPx pin output driver by setting the associated TRIS bit. Load the PRx register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value.
PIC16(L)F1847 24.3.6 PWM RESOLUTION EQUATION 24-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PRx is 255. The resolution is a function of the PRx register value as shown by Equation 24-4.
PIC16(L)F1847 24.3.7 OPERATION IN SLEEP MODE 24.3.10 In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 24.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1.
PIC16(L)F1847 24.4 PWM (Enhanced Mode) To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured appropriately. The enhanced PWM function described in this section is available for CCP modules ECCP1 and ECCP2 with any differences between modules noted. The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately.
PIC16(L)F1847 TABLE 24-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: PWM Steering enables outputs in Single mode.
PIC16(L)F1847 FIGURE 24-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal PRx+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay Delay PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5
PIC16(L)F1847 24.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 24-9). This mode can be used for Half-Bridge applications, as shown in Figure 24-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.
PIC16(L)F1847 24.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 24-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure 24-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure 24-12.
PIC16(L)F1847 FIGURE 24-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 24.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register.
PIC16(L)F1847 FIGURE 24-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: T = TOFF – TON All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 24.4.3 ENHANCED PWM AUTO-SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist.
PIC16(L)F1847 24.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register. FIGURE 24-15: If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCPxASE bit will be cleared via hardware and normal operation will resume.
PIC16(L)F1847 24.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 24-16: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC16(L)F1847 24.4.6 PWM STEERING MODE 24.4.6.1 In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM<3:2> = 11 and PxM<1:0> = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STRx bits of the PSTRxCON register, as shown in Register 24-5.
PIC16(L)F1847 24.4.8 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 “Alternate Pin Function” for more information.
PIC16(L)F1847 TABLE 24-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM Name APFCON0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL CCP1CON CCP1AS CCPTMRS INTCON P1M<1:0> DC1B<1:0> CCP1ASE CCP1AS<2:0> C4TSEL<1:0> C3TSEL<1:0> CCP1M<3:0> Register on Page 118 226 PSS1AC<1:0> PSS1BD<1:0> 228 C2TSEL<1:0> C1TSEL<1:0> 227 GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 88 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE
PIC16(L)F1847 REGISTER 24-1: R/W-00 CCPxCON: CCPx CONTROL REGISTER R/W-0/0 R/W-0/0 PxM<1:0>(1) R/W-0/0 R/W-0/0 DCxB<1:0> R/W-0/0 R/W-0/0 R/W-0/0 CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits(1) Capture mode: Unused Compare mode: Unused If CCPxM<
PIC16(L)F1847 REGISTER 24-2: R/W-0/0 CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER R/W-0/0 R/W-0/0 C4TSEL<1:0> R/W-0/0 R/W-0/0 C3TSEL<1:0> R/W-0/0 R/W-0/0 C2TSEL<1:0> bit 7 R/W-0/0 C1TSEL<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection 00 = CCP4 is based off Timer 2 in PWM M
PIC16(L)F1847 REGISTER 24-3: R/W-0/0 CCPxAS: CCPx AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 CCPxASE R/W-0/0 R/W-0/0 CCPxAS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 PSSxAC<1:0> R/W-0/0 PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occurred;
PIC16(L)F1847 REGISTER 24-4: R/W-0/0 PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 PxRSEN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxDC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown even
PIC16(L)F1847 PSTRxCON: PWM STEERING CONTROL REGISTER(1) REGISTER 24-5: U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering update oc
PIC16(L)F1847 25.0 25.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP1 AND MSSP2) MODULE Note: Master SSPx (MSSPx) Module Overview Register names, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices.
PIC16(L)F1847 The I2C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDAx hold times Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names.
PIC16(L)F1847 FIGURE 25-3: MSSPx BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 25.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select.
PIC16(L)F1847 FIGURE 25-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCKx SCKx SDOx SDIx SDIx SDOx General I/O General I/O SSx General I/O SCKx SDIx SDOx SPI Slave #1 SPI Slave #2 SSx SCKx SDIx SDOx SPI Slave #3 SSx 25.2.1 SPI MODE REGISTERS The MSSPx module has five registers for SPI mode operation.
PIC16(L)F1847 25.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC16(L)F1847 25.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2, Figure 25-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC16(L)F1847 25.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register.
PIC16(L)F1847 FIGURE 25-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDOx SDIx SDIx SDOx General I/O SPI Slave #1 SSx SCK SDIx SDOx SPI Slave #2 SSx SCK SDIx SDOx SPI Slave #3 SSx FIGURE 25-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 SDIx bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF 2011-201
PIC16(L)F1847 FIGURE 25-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 25-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit
PIC16(L)F1847 25.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSPx clock is much faster than the system clock. In Slave mode, when MSSPx interrupts are enabled, after the master completes sending data, an MSSPx interrupt will wake the controller from Sleep.
PIC16(L)F1847 25.3 I2C MODE OVERVIEW The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCLx The I2C bus specifies two signal connections: • Serial Clock (SCLx) • Serial Data (SDAx) Figure 25-2 and Figure 25-3 show the block diagrams of the MSSPx module when operating in I2C mode.
PIC16(L)F1847 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration.
PIC16(L)F1847 25.4 I2C MODE OPERATION All MSSPx I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I2C devices. 25.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a Master to a Slave or vice-versa, followed by an Acknowledge bit sent back.
PIC16(L)F1847 25.4.5 START CONDITION 25.4.7 2 The I C specification defines a Start condition as a transition of SDAx from a high to a low state while SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 25-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid.
PIC16(L)F1847 25.4.9 ACKNOWLEDGE SEQUENCE The 9h SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDAx line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
PIC16(L)F1847 25.5.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation.
DS40001453E-page 248 SSPOV BF SSPxIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
2011-2013 Microchip Technology Inc. CKP SSPOV BF SSPxIF 1 SCLx S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCLx SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
DS40001453E-page 250 P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPxIF is set 4 ACKTIM set by hardware on 8th falling edge of SCLx When AHEN=1: CKP is cleared by hardware and SCLx is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCLx When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCLx
2011-2013 Microchip Technology Inc.
PIC16(L)F1847 25.5.3 SLAVE TRANSMISSION 25.5.3.2 7-Bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the 9th bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission.
2011-2013 Microchip Technology Inc.
PIC16(L)F1847 25.5.3.3 7-Bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 25-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
2011-2013 Microchip Technology Inc. D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPxIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCLx 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC16(L)F1847 25.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSPx module configured as an I2C Slave in 10-bit Addressing mode. Figure 25-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled.
2011-2013 Microchip Technology Inc.
DS40001453E-page 258 ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCLx If when AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCLx SSPxBUF can be read anytime before the next received byte Cl
2011-2013 Microchip Technology Inc.
PIC16(L)F1847 25.5.6 CLOCK STRETCHING Clock stretching occurs when a device on the bus holds the SCLx line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCLx.
PIC16(L)F1847 FIGURE 25-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX ‚ – 1 DX SCLx Master device asserts clock CKP Master device releases clock WR SSPxCON1 25.5.8 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device.
PIC16(L)F1847 FIGURE 25-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDAx SCLx S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT<0>) Cleared by software GCEN (SSPxCON2<7>) SSPxBUF is read ’1’ 25.5.
PIC16(L)F1847 25.6 I2C MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDAx and SCKx pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions.
PIC16(L)F1847 25.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting.
PIC16(L)F1847 25.6.4 I2C MASTER MODE START CONDITION TIMING by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. To initiate a Start condition (Figure 25-26), the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count.
PIC16(L)F1847 25.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out.
PIC16(L)F1847 25.6.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted. SCLx is held low for one Baud Rate Generator rollover count (TBRG).
DS40001453E-page 268 S R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written by software Cleared by software service routine from SSPx interrupt 2 D6 Tra
PIC16(L)F1847 25.6.7 I2C MASTER MODE RECEPTION Master mode reception (Figure 25-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR.
DS40001453E-page 270 RCEN ACKEN SSPOV BF (SSPxSTAT<0>) SDAx = 0, SCLx = 1 while CPU responds to SSPxIF SSPxIF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDAx = ACKDT = 0 Cleared in sof
PIC16(L)F1847 25.6.8 ACKNOWLEDGE SEQUENCE TIMING 25.6.9 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the 9th clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16(L)F1847 FIGURE 25-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 25.6.
PIC16(L)F1847 FIGURE 25-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data does not match what is driven by the master. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 25.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 25-33). SCLx is sampled low before SDAx is asserted low (Figure 25-34). SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCLx pin is sampled as ‘0’ during this time, a bus collision does not occur.
PIC16(L)F1847 FIGURE 25-34: BUS COLLISION DURING START CONDITION (SCLX = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC16(L)F1847 25.6.13.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDAx when SCLx goes from low level to high level (Case 1). SCLx goes low before SDAx is asserted low, indicating that another master is attempting to transmit a data ‘1’ (Case 2). When the user releases SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero.
PIC16(L)F1847 FIGURE 25-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx BCLxIF SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. Interrupt cleared by software RSEN S ’0’ SSPxIF 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 25.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 25-38).
PIC16(L)F1847 TABLE 25-3: REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 88 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 89 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 90 SSP2IE 92 Name INTCON PIE4 — — — — — — BCL2IE PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 93 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 94
PIC16(L)F1847 25.7 BAUD RATE GENERATOR The MSSPx module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 25-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line.
PIC16(L)F1847 25.
PIC16(L)F1847 REGISTER 25-1: bit 0 SSPxSTAT: SSPx STATUS REGISTER (CONTINUED) BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty DS40001453E-page 282 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 REGISTER 25-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1
PIC16(L)F1847 REGISTER 25-3: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in
PIC16(L)F1847 REGISTER 25-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in
PIC16(L)F1847 REGISTER 25-5: R/W-1/1 SSPxMSK: SSPx MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD to detect I2C address match 0 = The received address bit
PIC16(L)F1847 26.
PIC16(L)F1847 FIGURE 26-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 +1 SPBRGH SPBRGL RSR Register MSb Pin Buffer and Control Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Rece
PIC16(L)F1847 26.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F1847 26.1.1.4 TSR Status 26.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 26.1.1.5 1. 2. 3.
PIC16(L)F1847 FIGURE 26-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Transmit Buffer Reg. Empty Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY Word 1 Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions.
PIC16(L)F1847 26.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 26-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16(L)F1847 26.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16(L)F1847 26.1.2.8 Asynchronous Reception Setup: 26.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 26.3 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5.
PIC16(L)F1847 TABLE 26-2: Name APFCON0 SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL 118 APFCON1 — — — — — — — TXCKSEL 118 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298 GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 88 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 89 PIR1 TMR1GIF ADIF RCIF TXIF SSP
PIC16(L)F1847 26.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 26-1: The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output.
PIC16(L)F1847 REGISTER 26-2: R/W-0/0 RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 SPEN RX9 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x (1) (1) ADDEN FERR OERR RX9D SREN CREN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX
PIC16(L)F1847 REGISTER 26-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud
PIC16(L)F1847 26.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer.
PIC16(L)F1847 TABLE 26-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: Name BAUDCON SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE AB
PIC16(L)F1847 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.
PIC16(L)F1847 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC16(L)F1847 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.
PIC16(L)F1847 26.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 26.3.3 “Auto-Wake-up on Break”). In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed.
PIC16(L)F1847 26.3.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC16(L)F1847 FIGURE 26-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC16(L)F1847 26.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC16(L)F1847 26.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F1847 FIGURE 26-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: ‘1’ ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
PIC16(L)F1847 TABLE 26-7: Name APFCON0 SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL 118 APFCON1 — — — — — — — TXCKSEL 118 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298 GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 88 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 89 PIR1 TMR1GIF ADIF RCIF
PIC16(L)F1847 26.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16(L)F1847 FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F1847 26.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16(L)F1847 26.4.2.3 EUSART Synchronous Slave Reception 26.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 26.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F1847 26.5 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 26.5.
PIC16(L)F1847 NOTES: DS40001453E-page 316 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 27.0 CAPACITIVE SENSING MODULE The Capacitive Sensing (CPS) module allows for an interaction with an end user without a mechanical interface. In a typical application, the CPS module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the CPS module.
PIC16(L)F1847 FIGURE 27-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM Oscillator Module VDD (1) + (2) - S CPSx (1) Analog Pin - (2) Q CPSCLK R + Internal References Ref- 0 0 1 Ref+ DAC 1 FVR CPSRM Note 1: 2: Module Enable and Power mode selections are not shown. Comparators remain active in Noise Detection mode. DS40001453E-page 318 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 27.1 Analog MUX The CPS module can monitor multiple inputs for the PIC device. See Register 27-2 for details on number of inputs and channel select. The capacitive sensing inputs are defined as CPSx, as applicable to device. To determine if a frequency change has occurred the user must: • Select the appropriate CPS pin by setting the appropriate CPSCH bits of the CPSCON1 register. • Set the corresponding ANSEL bit. • Set the corresponding TRIS bit. • Run the software algorithm.
PIC16(L)F1847 27.4 Current Ranges The capacitive sensing oscillator can operate in one of seven different power modes. The power modes are separated into two ranges; the low range and the high range. When the oscillator’s low range is selected, the fixed internal voltage references of the capacitive sensing oscillator are being used. When the oscillator’s high range is selected, the variable voltage references supplied by the FVR and DAC modules are being used.
PIC16(L)F1847 27.5 Timer Resources 27.7 To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base. 27.
PIC16(L)F1847 27.7.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed information on the software required for CPS module.
PIC16(L)F1847 REGISTER 27-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 U-0 CPSON CPSRM — — R/W-0/0 R/W-0/0 CPSRNG<1:0> R-0/0 R/W-0/0 CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSON: CPS Module Enable bit 1 = CPS module is enabled 0 = CPS module is disabled bit
PIC16(L)F1847 REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CPSCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits a
PIC16(L)F1847 TABLE 27-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 122 ANSELC — — — — — — — — — CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 323 CPSCON1 — — — — GIE PEIE TMR0IE INTE WPUEN INTEDG TMR0CS TMR0SE Name INTCON OPTION_REG T1CON TMR1CS<1:0> T1CKPS<1:0> CPSCH<3:0> IOCE TMR0IF PSA INTF 324 IOCF 88 PS<2:0> 175 T1O
PIC16(L)F1847 NOTES: DS40001453E-page 326 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications.
PIC16(L)F1847 Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 28-2. FIGURE 28-2: PICkit™ STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 2 3 4 5 6 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * DS40001453E-page 328 The 6-pin header (0.100" spacing) accepts 0.025" square pins. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 28-3 for more information.
PIC16(L)F1847 NOTES: DS40001453E-page 330 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16(L)F1847 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal)
PIC16(L)F1847 TABLE 29-3: DEVICE(S) ENHANCED INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f
PIC16(L)F1847 TABLE 29-3: DEVICE(S) ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS 2 2 2 2 2 2 2 2 BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Loa
PIC16(L)F1847 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND.
PIC16(L)F1847 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16(L)F1847 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16(L)F1847 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1847 LSLF Logical Left Shift MOVF f {,d} Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F1847 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: MOVLP Syntax: [ label ] MOV
PIC16(L)F1847 NOP MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None Syntax: [ label ] O
PIC16(L)F1847 RETFIE Return from Interrupt Syntax: [ label ] RETFIE k RETURN Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction.
PIC16(L)F1847 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1847 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the 8-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F1847 30.0 ELECTRICAL SPECIFICATIONS 30.1 Absolute Maximum Ratings(†) Ambient temperature under bias...................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC16F1847 ..................................................................
PIC16(L)F1847 30.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC16LF1847 VDDMIN (Fosc 16 MHz).......................................................................................................... +1.8V VDDMIN (Fosc 20 MHz)..........................................................................................................
PIC16(L)F1847 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16F1847 ONLY FIGURE 30-1: VDD (V) 5.5 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies. VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16LF1847 ONLY VDD (V) FIGURE 30-2: 3.6 2.5 1.
PIC16(L)F1847 30.3 DC Characteristics TABLE 30-1: SUPPLY VOLTAGE PIC16LF1847 Standard Operating Conditions (unless otherwise stated) PIC16F1847 Param. No. D001 Sym. VDD D001 VDD D002* VDR D002* Characteristic Min. Typ† Max. Units Conditions VDDMIN 1.8 2.5 — — VDDMAX 3.6 3.6 V V FOSC 16 MHz: FOSC 32 MHz (Note 2) 1.8 2.5 — — 5.5 5.5 V V FOSC 16 MHz: FOSC 32 MHz (Note 2) 1.
PIC16(L)F1847 FIGURE 30-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 TABLE 30-2: SUPPLY CURRENT (IDD)(1,2) PIC16LF1847 Standard Operating Conditions (unless otherwise stated) PIC16F1847 Param. No. Device Characteristics Conditions Min. Typ† Max. Units — 9.5 14 A 1.8 — 12.5 17 A 3.0 — 22 29 A 1.8 — 27 35 A 3.0 — 30 38 A 5.0 — 9.5 14 A 1.8 — 12.5 17 A 3.0 — 22 29 A 1.8 — 27 35 A 3.0 — 30 38 A 5.0 — 105 110 A 1.8 — 160 190 A 3.0 — 132 154 A 1.8 — 186 220 A 3.
PIC16(L)F1847 TABLE 30-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC16LF1847 Standard Operating Conditions (unless otherwise stated) PIC16F1847 Param. No. Device Characteristics Conditions Min. Typ† Max. Units — 260 338 A 1.8 — 415 540 A 3.0 — 300 325 A 1.8 — 486 515 A 3.0 — 520 550 A 5.0 — 10 16 A 1.8 — 12 18 A 3.0 — 21 28 A 1.8 — 25 34 A 3.0 — 28 36 A 5.0 D016 — 175 215 A 1.8 — 216 245 A 3.0 D016 — 175 200 A 1.
PIC16(L)F1847 TABLE 30-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC16LF1847 Standard Operating Conditions (unless otherwise stated) PIC16F1847 Param. No. Device Characteristics Conditions Min. Typ† Max. Units D019 — 3.50 3.70 mA 3.0 — 4.20 4.30 mA 5.0 D020 — 3.20 3.50 mA 3.0 — 3.70 3.90 mA 3.6 D020 — 3.30 3.60 mA 3.0 — 3.70 4.10 mA 5.0 D021 — 252 350 A 1.8 — 480 580 A 3.0 — 302 425 A 1.8 — 440 680 A 3.0 — 511 780 A 5.
PIC16(L)F1847 TABLE 30-3: POWER-DOWN CURRENTS (IPD)(1,2) PIC16LF1847 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1847 Low-Power Sleep Mode Param. No. Device Characteristics D022 D022 Min. Typ† Max. +85°C Max. +125°C Units — 0.02 1.0 2.4 — 0.03 1.5 3.0 — 15 35 — 18 40 Conditions VDD Note A 1.8 A 3.0 WDT, BOR and T1OSC disabled, all Peripherals Inactive 44 A 1.8 48 A 3.
PIC16(L)F1847 TABLE 30-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED) PIC16LF1847 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1847 Low-Power Sleep Mode Param. No. Device Characteristics D027 D027 D027A D027A D027B D027B D028 D028 D028B D028B * † Note 1: 2: 3: Conditions Min. Typ† Max. +85°C Max. +125°C Units — 2.0 6.0 8.0 A 1.8 — 5.0 9.0 12.0 A 3.0 — 21 41 45 A 1.8 — 23 47 55 A 3.0 VDD — 29 55 68 A 5.0 — 6.0 9.
PIC16(L)F1847 TABLE 30-4: DC CHARACTERISTICS: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. VIL Characteristic Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D030 with TTL buffer D030A D031 D032 D033 VIH — — 0.8 V 4.5V VDD 5.5V — — 0.15 VDD V 1.8V VDD 4.5V 2.0V VDD 5.5V with Schmitt Trigger buffer — — 0.2 VDD V with I2C™ levels — — 0.3 VDD V with SMBus levels — — 0.8 V 2.7V VDD 5.
PIC16(L)F1847 TABLE 30-5: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.
PIC16(L)F1847 TABLE 30-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 65.5 C/W 18-pin PDIP package 76.0 C/W 18-pin SOIC package 87.3 C/W 20-pin SSOP package 31.
PIC16(L)F1847 30.4 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F1847 FIGURE 30-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-7: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. OS01 Sym.
PIC16(L)F1847 TABLE 30-8: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. OS08 Sym. HFOSC OS08A MFOSC Freq. Tolerance Characteristic Internal Calibrated HFINTOSC Frequency(1) Internal Calibrated MFINTOSC Frequency(1) Min. Typ† Max. Units Conditions 2% — 16.0 — MHz 0°C TA +60°C, VDD 2.5V 3% — 16.0 — MHz 60°C TA +85°C, VDD 2.5V 5% — 16.0 — MHz -40°C TA +125°C 2% — 500 — MHz 0°C TA +60°C, VDD 2.
PIC16(L)F1847 TABLE 30-9: PLL CLOCK TIMING SPECIFICATIONS Operating Conditions (unless otherwise stated) 2.7V ≤ VDD ≤ 5.5V , -40°C ≤ TA ≤ + 125°C Param. Sym. No. Min. Typ† Max. Units FOSC Oscillator Frequency Range (Note 1) 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) — — 2 ms F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% % F10 Characteristic Conditions * These parameters are characterized but not tested.
PIC16(L)F1847 FIGURE 30-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 30-10: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions OS11 TosH2ckL FOSC to CLKOUT(1) — — 70 ns 3.3V VDD 5.
PIC16(L)F1847 FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O pins Note 1: Asserted low. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 TABLE 30-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max.
PIC16(L)F1847 FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 30-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min.
PIC16(L)F1847 FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 30-4 for load conditions. TABLE 30-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Param. Sym. No. CC01* TccL Characteristic CCPx Input Low Time CC02* TccH CCPx Input High Time CC03* TccP CCPx Input Period Typ† Max. Units ns No Prescaler 0.5TCY + 20 — — With Prescaler 20 — — ns No Prescaler 0.
PIC16(L)F1847 TABLE 30-14: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — ±1 ±1.7 AD03 EDL Differential Error — ±1 — AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V AD05 EGN — ±1 ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage(4) 1.
PIC16(L)F1847 FIGURE 30-12: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 FIGURE 30-13: ADC CONVERSION TIMING (ADC CLOCK FROM FRC) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 2 1 0 NEW_DATA 1 TCY ADIF GO Sample 3 DONE AD132 Sampling Stopped Note 1: If the ADC clock source is selected a
PIC16(L)F1847 TABLE 30-16: COMPARATOR SPECIFICATIONS(1) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. Sym. Characteristics Min. Typ. Max. Units — ±7.
PIC16(L)F1847 FIGURE 30-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 30-4 for load conditions. TABLE 30-18: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol US120 TCKH2DTV US121 US122 TCKRF TDTRF FIGURE 30-15: Characteristic Min. Max. Units Conditions SYNC XMIT (Master and Slave) Clock high to data-out valid — 80 ns 3.0V VDD 5.5V — 100 ns 1.
PIC16(L)F1847 FIGURE 30-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDOx LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-4 for load conditions.
PIC16(L)F1847 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE = 0) SSx SP70 SCKx (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 MSb SDOx LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-4 for load conditions.
PIC16(L)F1847 TABLE 30-20: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Typ† Max. Units 2.
PIC16(L)F1847 I2C™ BUS START/STOP BITS TIMING FIGURE 30-20: SCLx SP93 SP91 SP90 SP92 SDAx Stop Condition Start Condition Note: Refer to Figure 30-4 for load conditions. TABLE 30-21: I2C™ BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic SP90* TSU:STA Start condition SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Typ 4700 — Max.
PIC16(L)F1847 FIGURE 30-21: I2C™ BUS DATA TIMING SP103 SCLx SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDAx In SP92 SP110 SP109 SP109 SDAx Out Note: Refer to Figure 30-4 for load conditions. 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 TABLE 30-22: I2C™ BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.
PIC16(L)F1847 TABLE 30-23: CAP SENSE OSCILLATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol CS01* ISRC CS02* Characteristic Current Source ISNK Current Sink CS03* VCTH Cap Threshold CS04* VCTL Cap Threshold CS05* VCHYST CAP HYSTERESIS (VCTH - VCTL) * † Note 1: Min. Typ† Max. Units Conditions High — -8 — A (Note 1) Medium — -1.5 — A (Note 1) Low — -0.3 — A (Note 1) High — 7.5 — A (Note 1) Medium — 1.
PIC16(L)F1847 NOTES: DS40001453E-page 378 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16(L)F1847 FIGURE 31-1: IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16LF1847 ONLY 20 Max: 85°C + 3ı Typical: 25°C Max. 15 IDD (μA) Typical 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16F1847 ONLY FIGURE 31-2: 40 Max. Max: 85°C + 3ı Typical: 25°C 35 Typical 30 IDD (μA) 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001453E-page 380 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1847 ONLY 600 4 MHz XT Typical: 25°C 500 IDD (μA) 400 4 MHz EXTRC 300 200 1 MHz XT 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.6 3.8 VDD (V) FIGURE 31-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1847 ONLY 700 4 MHz XT 600 Max: 85°C + 3ı IDD (μA) 500 4 MHz EXTRC 400 300 1 MHz XT 200 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1847 ONLY 600 4 MHz EXTRC Typical: 25°C 500 4 MHz XT IDD (μA) 400 300 1 MHz XT 200 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1847 ONLY FIGURE 31-6: 900 Max: 85°C + 3ı 800 4 MHz EXTRC 700 IDD (μA) 600 4 MHz XT 500 400 1 MHz XT 300 200 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001453E-page 382 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-7: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1847 ONLY 450 Typical: 25°C 400 4 MHz 350 IDD (μA) 300 250 200 150 100 50 1 MHz 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-8: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1847 ONLY 600 Max: 85°C + 3ı 500 4 MHz IDD (μA) 400 300 200 1 MHz 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-9: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1847 ONLY 600 Typical: 25°C 500 4 MHz IDD (μA) 400 300 200 1 MHz 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 31-10: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1847 ONLY 600 Max: 85°C + 3ı 500 4 MHz IDD (μA) 400 300 1 MHz 200 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001453E-page 384 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-11: IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16LF1847 ONLY 20 Max. IDD (μA) 15 Typical 10 5 Max: 85°C + 3ı Typical: 25°C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-12: IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16F1847 ONLY 40 35 Max. IDD (μA) 30 25 Typical 20 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-13: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16LF1847 ONLY 260 Max: 85°C + 3ı Typical: 25°C 240 Max. 220 Typical IDD (μA) 200 180 160 140 120 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-14: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16F1847 ONLY 260 Max: 85°C + 3ı Typical: 25°C 240 Max. 220 IDD (μA) 200 Typical 180 160 140 120 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1847 FIGURE 31-15: IDD TYPICAL, HFINTOSC MODE, PIC16LF1847 ONLY 4.0 Typical: 25°C 3.5 IDD (mA) 3.0 2.5 16 MHz 2.0 8 MHz 1.5 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.4 3.6 3.8 VDD (V) FIGURE 31-16: IDD MAXIMUM, HFINTOSC MODE, PIC16LF1847 ONLY 4.0 Typical: 25°C 3.5 IDD (mA) 3.0 2.5 16 MHz 2.0 8 MHz 1.5 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-17: IDD TYPICAL, HFINTOSC MODE, PIC16F1847 ONLY 4.5 32 MHz (PLL) 4.0 Typical: 25°C 3.5 IDD (mA) 3.0 16 MHz 2.5 2.0 8 MHz 1.5 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 4.5 5.0 5.5 VDD (V) IDD MAXIMUM, HFINTOSC MODE, PIC16F1847 ONLY FIGURE 31-18: 5.0 Max: 85°C + 3ı 4.5 32 MHz (PLL) 4.0 3.5 IDD (mA) 3.0 16 MHz 2.5 8 MHz 2.0 1.5 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 VDD (V) DS40001453E-page 388 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-19: IDD, HS OSCILLATOR, 32 MHz (8 MHz + 4x PLL), PIC16LF1847 ONLY 4.5 Max: 85°C + 3ı Typical: 25°C 4.0 Max 3.5 Typical IDD (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-20: IDD, HS OSCILLATOR, 32 MHz (8 MHz + 4x PLL), PIC16F1847 ONLY 4.5 Max Max: 85°C + 3ı Typical: 25°C 4.0 3.5 Typical 3.0 IDD (mA) 2.5 2.0 1.5 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1847 FIGURE 31-21: IPD BASE, LOW-POWER SLEEP MODE, PIC16LF1847 ONLY 1.60 Max: 85°C + 3ı Typical: 25°C 1.40 Max. IPD (μA) 1.20 1.00 0.80 0.60 0.40 0.20 Typical 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-22: IPD BASE, LOW-POWER SLEEP MODE, PIC16F1847 ONLY 50 Max: 85°C + 3ı Typical: 25°C 45 Max. 40 IPD D (μA) 35 30 25 Typical 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1847 FIGURE 31-23: IPD, WATCHDOG TIMER (WDT), PIC16LF1847 ONLY 2.5 Max. Max: 85°C + 3ı Typical: 25°C IPD (μA (μA) 2 1.5 1 Typical 0.5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-24: IPD, WATCHDOG TIMER (WDT), PIC16F1847 ONLY 50 Max: 85°C + 3ı Typical: 25°C 45 Max. 40 IPD (μ (μA) 35 30 25 Typical 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-25: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1847 ONLY 30 25 Max. 20 IPD (μA (μA) Typical 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-26: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1847 ONLY 140 Max: 85°C + 3ı Ma Typical: 25°C 120 IPD (μ (μA) 100 Max. 80 Typical 60 40 20 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001453E-page 392 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-27: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1847 ONLY 16 M Max. Max: 85°C + 3ı Typical: 25°C 14 IPD (μA) μA) 12 10 Typical 8 6 4 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-28: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16F1847 ONLY 60 Max Max. 50 IPD (μA) 40 Typical 30 20 Max: 85°C + 3ı Typical: 25°C 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-29: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16LF1847 ONLY 6.0 Max Max. Max: 85°C + 3ı Typical: 25°C 5.0 IPD (μA (μA) 4.0 3.0 Typical 2.0 1.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-30: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16F1847 ONLY 60 Max. 50 IPD (μ (μA) 40 30 Typical 20 Max: 85°C + 3ı Typical: 25°C 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1847 FIGURE 31-31: IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE, CPSRM = 0, CPSRNG = 01, PIC16LF1847 ONLY 10 Max: 85°C + 3ı Typical: 25°C IPD (μA (μA) 8 Max. 6 Typical 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-32: IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE, CPSRM = 0, CPSRNG = 01, PIC16F1847 ONLY 60 Max Max. Max: 85°C + 3ı Typical: 25°C 50 IPD (μA (μA) 40 30 Typical 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
PIC16(L)F1847 FIGURE 31-33: IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE, CPSRM = 0, CPSRNG = 10, PIC16LF1847 ONLY 14 Max: 85°C + 3ı Typical: 25°C 12 Max. IPD D (μA) 10 8 Typical 6 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-34: IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE, CPSRM = 0, CPSRNG = 10, PIC16F1847 ONLY 60 Max. 50 IPD (μA (μA) 40 30 T i l Typical 20 Max: 85°C + 3ı Typical: 25°C 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.
PIC16(L)F1847 FIGURE 31-35: IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE, CPSRM = 0, CPSRNG = 11, PIC16LF1847 ONLY 70 Max: 85°C + 3 M 3ı Typical: 25°C 60 Max. IPD (μA (μA) 50 40 30 Typical 20 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-36: IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE, CPSRM = 0, CPSRNG = 11, PIC16F1847 ONLY 90 Max: 85°C + 3ı Typical: 25°C 80 Max. 70 IPD (μA (μA) 60 Typical yp 50 40 30 20 10 0 1.5 2.0 2.5 3.
PIC16(L)F1847 FIGURE 31-37: IPD, COMPARATOR, LOW-POWER MODE, CxSP = 0, PIC16LF1847 ONLY 20 Max. IPD ((μA) 15 10 Typical 5 Max: 85°C + 3ı Typical: 25°C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-38: IPD, COMPARATOR, LOW-POWER MODE, CxSP = 0, PIC16F1847 ONLY 70 M Max. 60 IPD (μ (μA) 50 40 Typical 30 20 Max: 85°C + 3ı Typical: 25°C 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001453E-page 398 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-39: IPD, COMPARATOR, NORMAL-POWER MODE, CxSP = 1, PIC16LF1847 ONLY 60 Max. 50 IPD (μA (μA) 40 Typical 30 20 Max: 85°C + 3ı Typical: 25°C 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-40: IPD, COMPARATOR, NORMAL-POWER MODE, CxSP = 1, PIC16F1847 ONLY 100 Max. 90 80 70 Typical IPD (μA (μA) 60 50 40 30 20 Max: 85°C + 3ı Typical: 25 C 25°C 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-41: VOH vs. IOH OVER TEMPERATURE, VDD = 5.0V, PIC16F1847 ONLY 6 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 5 VOH (V) 4 Min. (-40°C) 3 2 Typical (25°C) 1 Max. (125°C) 0 -30 -25 -20 -15 -10 -5 0 IOH (mA) VOL vs. IOL OVER TEMPERATURE, VDD = 5.0V, PIC16F1847 ONLY FIGURE 31-42: 5 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı VOL (V) 4 3 Max. (125°C) Min.
PIC16(L)F1847 FIGURE 31-43: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 3.0 VOH (V) 2.5 2.0 1.5 Min. (-40°C) Typical (25°C) Max. (125°C) 1.0 0.5 0.0 -14 -12 -10 -8 -6 -4 -2 0 IOH (mA) FIGURE 31-44: VOL vs. IOL, OVER TEMPERATURE, VDD = 3.0V 3.0 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 2.5 VOL (V) 2.0 Max. (125°C) Typical (25°C) Min. (-40°C) 1.5 1.0 0.5 0.0 0 5 10 15 20 25 30 IOL (mA) 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-45: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V 2.0 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 1.8 1.6 VOH (V) 1.4 1.2 1.0 Typical (25°C) Min. (-40°C) 0.8 Max. (125°C) 0.6 0.4 0.2 0.0 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IOH (mA) VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V FIGURE 31-46: 1.8 1.6 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 1.4 VOL (V) 1.2 1.0 Max. (125°C) Min. (-40°C) Typical (25°C) 0.8 0.6 0.4 0.2 0.
PIC16(L)F1847 FIGURE 31-47: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 Voltage (V) 1.64 Typical 1.62 Min. 1.60 1.58 1.56 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.54 1.52 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 31-48: POR REARM VOLTAGE, PIC16F1847 ONLY 1.54 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.52 1.50 Max. Voltage (V) 1.48 1.46 1.44 Typical 1.42 1.40 Min. 1.38 1.36 1.
PIC16(L)F1847 FIGURE 31-49: BROWN-OUT RESET VOLTAGE, BORV = 1 2.10 Max: Typical + 3ı Min: Typical - 3ı 2.05 2.00 Voltage (V) Max. 1.95 1.90 Min. 1.85 1.80 1.75 1.70 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-50: BROWN-OUT RESET HYSTERESIS, BORV = 1 70 Max. 60 Voltage (mV) 50 Typical 40 30 Min.
PIC16(L)F1847 FIGURE 31-51: BROWN-OUT RESET VOLTAGE, BORV = 0 2.90 2.85 Max: Typical + 3ı Min: Typical - 3ı 2.80 Max. Voltage (V) 2.75 2.70 2.65 Min. 2.60 2.55 2.50 2.45 2.40 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-52: BROWN-OUT RESET HYSTERESIS, BORV = 0 90 80 Max. 70 Voltage (mV) 60 50 Typical 40 30 20 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı Min.
PIC16(L)F1847 FIGURE 31-53: WDT TIME-OUT PERIOD 24 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 22 Max. Time (ms) 20 18 Typical 16 14 Min. 12 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-54: PWRT PERIOD 110 100 Max. Time (ms) 90 80 Typical 70 Min. 60 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 50 40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1847 FIGURE 31-55: COMPARATOR HYSTERESIS, NORMAL-POWER MODE, CxSP = 1, CxHYS = 1 80 70 Max. Hysteresis (mV) 60 Typical 50 40 Min. 30 20 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-56: COMPARATOR HYSTERESIS, LOW-POWER MODE, CxSP = 0, CxHYS = 1 16 14 Max. Hysteresis (mV) 12 Typical 10 8 6 Min. 4 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1847 FIGURE 31-57: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE, CxSP = 1 350 300 Time (ns) 250 Max. 200 Typical 150 100 Max: Typical + 3ı Typical: 25°C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-58: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER MODE, CxSP = 1 400 350 Max: 125°C + 3ı Typical: 25°C Min: -45°C - 3ı Time (ns) 300 250 Max. (125°C) 200 150 Typical (25°C) 100 Min. (-40°C) 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1847 FIGURE 31-59: COMPARATOR INPUT OFFSET AT 25°C, NORMAL-POWER MODE, CxSP = 1, PIC16F1847 ONLY 50 40 30 Max. Offset Voltage (mV) 20 10 Typical 0 Min. -10 -20 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı -30 -40 -50 0.0 1.0 2.0 3.0 4.0 5.0 Common Mode Voltage (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 FIGURE 31-60: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1847 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 Min. 26 24 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1847 ONLY FIGURE 31-61: 36 34 Max. Frequency (kHz) 32 30 Typical 28 26 Min.
PIC16(L)F1847 FIGURE 31-62: CAP SENSE CURRENT SINK/SOURCE CHARACTERISTICS FIXED VOLTAGE REFERENCE (CPSRM = 0), HIGH CURRENT RANGE (CPSRNG = 11) 20 15 IPIN (uA) Sink Typical Sink Max. 10 Sink Min. 5 0 -5 Source Min. -10 Source Max. -15 Max: Typical + 3ı Typical: Min: Typical - 3ı Source Typical -20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.
PIC16(L)F1847 FIGURE 31-64: CAP SENSE CURRENT SINK/SOURCE CHARACTERISTICS FIXED VOLTAGE REFERENCE (CPSRM = 0), LOW CURRENT RANGE (CPSRNG = 01) 0.8 Sink Max. 0.6 Sink Typical 0.4 Sink Min. IPIN (uA) 0.2 0.0 -0.2 Source Min. -0.4 Source Typical -0.6 Source Max. -0.8 -1.0 Max: Typical + 3ı Typical: Min: Typical - 3ı -1.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) \ DS40001453E-page 412 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 32.
PIC16(L)F1847 32.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 32.
PIC16(L)F1847 32.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F1847 32.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 32.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F1847 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 18-Lead PDIP (.300”) Example PIC16F1847 -E/P e3 1235017 18-Lead SOIC (.300”) Example PIC16 F1847 -E/SO e3 1235017 20-Lead SSOP Example PIC16F1847 -E/SS e3 1235017 28-Lead QFN (6x6 mm) PIN 1 Example PIN 1 XXXXXXXX XXXXXXXX YYWWNNN 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 28-Lead UQFN PIN 1 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: * Example PIC16 F1847 E/MV e3 235017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
PIC16(L)F1847 33.2 Package Details The following sections give the technical details of the packages.
PIC16(L)F1847 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001453E-page 420 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001453E-page 422 2011-2013 Microchip Technology Inc.
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PIC16(L)F1847 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001453E-page 424 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 DS40001453E-page 426 2011-2013 Microchip Technology Inc.
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PIC16(L)F1847 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001453E-page 428 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 DS40001453E-page 430 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (January 2011) Revision B (May 2011) Added Operating Current Value; Updated the Electrical Specifications section; Updated the Packaging Information section; Other minor corrections. Revision C (November 2012) Specifications MIGRATING FROM OTHER PIC® DEVICES This section provides comparisons when migrating from other similar PIC® devices to the PIC16(L)F1847 family of devices. Original release of this document.
PIC16(L)F1847 NOTES: DS40001453E-page 432 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16(L)F1847 NOTES: DS40001453E-page 434 2011-2013 Microchip Technology Inc.
PIC16(L)F1847 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
PIC16(L)F1847 NOTES: DS40001453E-page 436 2011-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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