Datasheet

PIC16(L)F1825/1829
DS41440C-page 328 2010-2012 Microchip Technology Inc.
TABLE 27-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0 U-0 U-0 U-0 R/W-0/0
(1)
R/W-0/0 R/W-0/0 R/W-0/0
CPSCH<3:2> CPSCH<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as0
bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits
If CPSON =
0:
These bits are ignored. No channel is selected.
If CPSON = 1:
0000 = channel 0, (CPS0)
0001 = channel 1, (CPS1)
0010 = channel 2, (CPS2)
0011 = channel 3, (CPS3)
0100 = channel 4, (CPS4)
0101 = channel 5, (CPS5)
0110 = channel 6, (CPS6)
0111 = channel 7, (CPS7)
1000 = channel 8, (CPS4)
(1)
1001 = channel 9, (CPS5)
(1)
1010 = channel 10, (CPS6)
(1)
1011 = channel 11, (CPS7)
(1)
1100 = Reserved. Do not use.
1111 = Reserved. Do not use.
Note 1: These channels are only implemented on the PIC16(L)F1829.
Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Register on
Page
ANSELA ANSA4 ANSA2 ANSA1 ANSA0
126
ANSELC ANSC7
(1)
ANSC6
(1)
ANSC3 ANSC2 ANSC1 ANSC0
137
CPSCON0 CPSON
CPSRM CPSRNG<1:0> CPSOUT T0XCS
327
CPSCON1
—CPSCH<3:0>
328
INLVLA
INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 127
INLVLB
(1)
INLVLB7 INLVLB6 INLVLB5 INLVLB4 132
INLVLC INLVLC7
(1)
INLVLC6
(1)
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 138
INTCON GIE PEIE TMR0IE
INTE IOCIE TMR0IF INTF IOCIF
90
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 185
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—TMR1ON
195
TRISA
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
125
TRISB
(1)
TRISB7 TRISB6 TRISB5 TRISB4 131
TRISC TRISC7
(1)
TRISC6
(1)
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
136
Legend: — Unimplemented locations, read as ‘0’. Shaded cells are not used by the CPS module.
Note 1: PIC16(L)F1829 only.