Datasheet

 2010-2012 Microchip Technology Inc. DS41440C-page 301
PIC16(L)F1825/1829
TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
Page
APFCON0 RXDTSEL
SDO1SEL
(2)
SS1SEL
(2)
— T1GSEL TXCKSEL — —
121
BAUDCON
ABDOVF RCIDL — SCKP BRG16 —WUEABDEN 304
INLVLA
(3)
— — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 127
INLVLB
(1)
INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 132
INLVLC
INLVLC7
(1)
INLVLC6
(1)
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 138
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 91
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
95
RCREG EUSART Receive Data Register 298*
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 303
SPBRGL SPBRG<7:0> 305*
SPBRGH SPBRG<15:8> 305*
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
125
TRISB
(1)
TRISB7 TRISB6 TRISB5 TRISB4 — — — —
131
TRISC
TRISC7
(1)
TRISC6
(1)
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
136
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 302
Legend: — Unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.
* Page provides register information.
Note 1: PIC16(L)F1829 only.
2: PIC16(L)F1825 only.
3: Unshaded cells apply to PIC16(L)F1825 only.