Datasheet

 2010-2012 Microchip Technology Inc. DS41440C-page 215
PIC16(L)F1825/1829
24.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (F
OSC/4), or by an external clock source.
When Timer1 is clocked by F
OSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
24.1.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default
locations are upon a Reset, see
Section 12.1
“Alternate Pin Function”
for more information.
TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
Page
APFCON1 — — SDO2SEL
(2)
SS2SEL
(2)
P1DSEL P1CSEL P2BSEL CCP2SEL 122
CCP1CON P1M<1:0>
(1)
DC1B<1:0> CCP1M<3:0>
236
CCP2CON P2M<1:0>
(1)
DC2B<1:0> CCP2M<3:0>
236
CCP3CON
— — DC3B<1:0> CCP3M<3:0>
236
CCP4CON
— — DC4B<1:0> CCP4M<3:0>
236
CCPRxL Capture/Compare/PWM Register x Low Byte (LSB)
214*
CCPRxH Capture/Compare/PWM Register x High Byte (MSB)
214*
CMxCON0 CxON CxOUT CxOE CxPOL
— CxSP CxHYS CxSYNC
179
CMxCON1 CxINTP CxINTN CxPCH<1:0>
— — CxNCH<1:0>
180
INLVLA
— — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 127
INLVLC
INLVLC7
(2)
INLVLC6
(2)
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 138
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
90
PIE1 TMR1GIE
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 91
PIE2
OSFIE C2IE C1IE EEIE BCL1IE
—
— CCP2IE 92
PIE3
— — CCP4IE CCP3IE TMR6IE —TMR4IE— 93
PIR1
TMR1GIF
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
95
PIR2
OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF
96
PIR3
— — CCP4IF CCP3IF TMR6IF —TMR4IF— 97
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
—TMR1ON
195
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE
T1GVAL T1GSS<1:0>
196
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
191*
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
191*
TRISA
— —
TRISA5
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
125
TRISC
TRISC7
(2)
TRISC6
(2)
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
136
Legend: — Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.
* Page provides register information.
Note 1: Applies to ECCP modules only.
2: PIC16(L)F1829 only.