Datasheet

PIC16(L)F1824/1828
DS41419D-page 8 2010-2012 Microchip Technology Inc.
TABLE 2: 20-PIN ALLOCATION TABLE (PIC16(L)F1828)
I/O
20-Pin DIP/SOIC/SSOP
20-Pin QFN
A/D
Reference
Cap Sense
Comparator
SR Latch
Timers
CCP
EUSART
SSP
Interrupt
Modulator
Pull-up
Basic
RA0 19 16 AN0 VREF-
DACOUT
CPS0 C1IN+ IOC Y ICSPDAT/
ICDDAT
RA1 18 15 AN1 VREF+ CPS1 C12IN0- SRI IOC Y ICSPCLK/
ICDCLK
RA2 17 14 AN2 CPS2 C1OUT SRQ T0CKI CCP3
FLT0
INT/
IOC
Y
RA3 4 1 T1G
(1)
IOC Y
(4)
MCLR
VPP
RA4 3 20 AN3 CPS3 T1G
(1)
T1OSO
P2B
(1)
IOC Y OSC2
CLKOUT
CLKR
RA5 2 19 T1CKI
T1OSI
CCP2
(1)
P2A
(1)
IOC Y OSC1
CLKIN
RB4 13 10 AN10 CPS10 SDA1
SDI1
IOC Y
RB5 12 9 AN11 CPS11 RX
(1)
DT
(1)
IOC Y
RB6 11 8 SCL1
SCK1
IOC Y
RB7 10 7 TX
(1)
CK
(1)
IOC Y
RC0 16 13 AN4 CPS4 C2IN+ P1D
(1)
Y
RC1 15 12 AN5 CPS5 C12IN1- —P1C
(1)
Y
RC2 14 11 AN6 CPS6 C12IN2- P1D
(1)
P2B
(1)
MDCIN1 Y
RC3 7 4 AN7 CPS7 C12IN3- P1C
(1)
CCP2
(1)
P2A
(1)
—MDMIN Y
RC4 6 3 C2OUT SRNQ P1B TX
(1)
CK
(1)
MDOUT Y
RC5 5 2 CCP1
P1A
RX
(1)
DT
(1)
MDCIN2 Y
RC6 8 5 AN8 CPS8 CCP4
SS
Y
RC7 9 6 AN9 CPS9 SDO Y
VDD 1 18 VDD
Vss 20 17 VSS
Note 1: Pin function is selectable via the APFCON0 or APFCON1 registers.