Datasheet
PIC16(L)F1824/1828
DS41419D-page 448 2010-2012 Microchip Technology Inc.
SUBWFB........................................................................... 351
T
T1CON Register.......................................................... 31, 197
T1GCON Register............................................................. 198
T2CON Register.................................................................. 31
T4CON Register.................................................................. 39
T6CON Register.................................................................. 39
Temperature Indicator Module ..........................................149
Thermal Considerations ....................................................365
Timer0............................................................................... 185
Associated Registers ................................................188
Operation ..................................................................185
Specifications............................................................373
Timer1............................................................................... 189
Associated registers.................................................. 199
Asynchronous Counter Mode ................................... 191
Reading and Writing ......................................... 191
Clock Source Selection............................................. 190
Interrupt..................................................................... 193
Operation ..................................................................190
Operation During Sleep ............................................ 193
Oscillator ................................................................... 191
Prescaler...................................................................191
Specifications............................................................373
Timer1 Gate
Selecting Source............................................... 191
TMR1H Register .......................................................189
TMR1L Register........................................................189
Timer2
Associated registers.................................................. 204
Timer2/4/6.........................................................................201
Associated registers.................................................. 204
Timers
Timer1
T1CON..............................................................197
T1GCON...........................................................198
Timer2/4/6
TXCON .............................................................203
Timing Diagrams
A/D Conversion.........................................................375
A/D Conversion (Sleep Mode) .................................. 375
Acknowledge Sequence ........................................... 283
Asynchronous Reception .......................................... 306
Asynchronous Transmission ..................................... 302
Asynchronous Transmission (Back to Back) ............ 303
Auto Wake-up Bit (WUE) During Normal Operation . 318
Auto Wake-up Bit (WUE) During Sleep .................... 318
Automatic Baud Rate Calibration.............................. 316
Baud Rate Generator with Clock Arbitration ............. 276
BRG Reset Due to SDA Arbitration During Start
Condition........................................................... 287
Brown-out Reset (BOR) ............................................ 371
Brown-out Reset Situations ........................................ 79
Bus Collision During a Repeated Start Condition
(Case 1) ............................................................ 288
Bus Collision During a Repeated Start Condition
(Case 2) ............................................................ 289
Bus Collision During a Start Condition (SCL = 0) .....287
Bus Collision During a Stop Condition (Case 1) ....... 290
Bus Collision During a Stop Condition (Case 2) ....... 290
Bus Collision During Start Condition (SDA only) ...... 286
Bus Collision for Transmit and Acknowledge............ 285
CLKOUT and I/O....................................................... 369
Clock Synchronization .............................................. 273
Clock Timing ............................................................. 367
Comparator Output ................................................... 177
Enhanced Capture/Compare/PWM (ECCP)............. 373
Fail-Safe Clock Monitor (FSCM)................................. 69
First Start Bit Timing ................................................. 277
Full-Bridge PWM Output........................................... 229
Half-Bridge PWM Output .................................. 227, 234
I
2
C Bus Data............................................................. 381
I
2
C Bus Start/Stop Bits ............................................. 381
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 280
I
2
C Master Mode (7-Bit Reception)........................... 282
I
2
C Stop Condition Receive or Transmit Mode......... 284
INT Pin Interrupt ......................................................... 91
Internal Oscillator Switch Timing ................................ 64
PWM Auto-shutdown................................................ 233
Firmware Restart .............................................. 232
PWM Direction Change ............................................ 230
PWM Direction Change at Near 100% Duty Cycle... 231
PWM Output (Active-High) ....................................... 225
PWM Output (Active-Low) ........................................ 226
Repeat Start Condition ............................................. 278
Reset Start-up Sequence ........................................... 82
Reset, WDT, OST and Power-up Timer ................... 370
Send Break Character Sequence............................. 319
SPI Master Mode (CKE = 1, SMP = 1) ..................... 378
SPI Mode (Master Mode).......................................... 250
SPI Slave Mode (CKE = 0) ....................................... 379
SPI Slave Mode (CKE = 1) ....................................... 379
Synchronous Reception (Master Mode, SREN) ....... 323
Synchronous Transmission ...................................... 321
Synchronous Transmission (Through TXEN) ........... 321
Timer0 and Timer1 External Clock ........................... 372
Timer1 Incrementing Edge ....................................... 193
Two Speed Start-up.................................................... 67
USART Synchronous Receive (Master/Slave) ......... 377
USART Synchronous Transmission (Master/Slave). 376
Wake-up from Interrupt............................................. 102
Timing Diagrams and Specifications
PLL Clock ................................................................. 368
Timing Parameter Symbology .......................................... 366
Timing Requirements
I
2
C Bus Data............................................................. 382
SPI Mode .................................................................. 380
TINLVLC Register............................................................. 139
TMR0 Register.................................................................... 31
TMR1H Register ................................................................. 31
TMR1L Register.................................................................. 31
TMR2 Register.................................................................... 31
TMR4 Register.................................................................... 39
TMR6 Register.................................................................... 39
TRIS.................................................................................. 352
TRISA Register........................................................... 32, 126
TRISB ............................................................................... 130
TRISB Register........................................................... 32, 132
TRISC............................................................................... 135
TRISC Register........................................................... 32, 137
Two-Speed Clock Start-up Mode........................................ 66
TXCON (Timer2/4/6) Register .......................................... 203
TXREG ............................................................................. 301
TXREG Register................................................................. 34
TXSTA Register.......................................................... 34, 308
BRGH Bit .................................................................. 311
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 377