Datasheet

PIC16(L)F1824/1828
DS41419D-page 104 2010-2012 Microchip Technology Inc.
10.1 Independent Clock Source
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator.
10.2 WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word 1. See Table 10-1.
10.2.1 WDT IS ALWAYS ON
When the WDTE bits of Configuration Word 1 are set to
11’, the WDT is always on.
WDT protection is active during Sleep.
10.2.2 WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Word 1 are set to
10’, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
10.2.3 WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Word 1 are set to
01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See
Table 10-1 for more details.
TABLE 10-1: WDT OPERATING MODES
10.3 Time-Out Period
The WDTPS bits of the WDTCON register set the
time-out period from 1ms to 256 seconds. After a
Reset, the default time-out period is 2 seconds.
10.4 Clearing the WDT
The WDT is cleared when any of the following
conditions occur:
•Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail event
WDT is disabled
•OST is running
See Table 10-2 for more information.
10.5 Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator
Module (With Fail-Safe Clock Monitor)” for more
information on the OST.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO
and PD bits
in the STATUS register are changed to indicate the
event. See Section 3.0 “Memory Organization” and
The STATUS register (Register 3-1) for more
information.
WDTE
Config bits
SWDTEN
Device
Mode
WDT
Mode
WDT_ON (11) X XActive
WDT_NSLEEP (10) X Awake Active
WDT_NSLEEP (10) X Sleep Disabled
WDT_SWDTEN (01) 1 XActive
WDT_SWDTEN (01) 0 XDisabled
WDT_OFF (00) X XDisabled
TABLE 10-2: WDT CLEARING CONDITIONS
Conditions WDT
WDTE<1:0> = 00
Cleared
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected