Datasheet

PIC16(L)F1826/27
DS41391D-page 176  2011 Microchip Technology Inc.
20.2 Option and Timer0 Control Register
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
REGISTER 20-1: OPTION_REG: OPTION REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 WPUEN
: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR
, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F
OSC/4)
bit 4 TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
CPSCON0
CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS
318
INTCON GIE PEIE TMR0IE
INTE IOCIE TMR0IF INTF IOCIF
86
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0
177
TMR0 Timer0 Module Register
173*
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
122
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit Value Timer0 Rate