Datasheet

PIC16(L)F1826/27
DS41391D-page 28  2011 Microchip Technology Inc.
TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx
00Dh PORTB
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx
00Eh
— Unimplemented — —
00Fh
— Unimplemented — —
010h
— Unimplemented — —
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF
— —CCP2IF
(1)
0000 0--0 0000 0--0
013h PIR3
(1)
— — CCP4IF CCP3IF TMR6IF — TMR4IF — --00 0-0- --00 0-0-
014h PIR4
(1)
— — — — — — BCL2IF SSP2IF ---- --00 ---- --00
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—TMR1ON0000 00-0 uuuu uu-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111
01Ch T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
01Dh
— Unimplemented — —
01Eh CPSCON0 CPSON
— — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000
01Fh CPSCON1
— — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000
Bank 1
08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
08Eh
— Unimplemented — —
08Fh
— Unimplemented — —
090h
— Unimplemented — —
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE
— — CCP2IE
(1)
0000 0--0 0000 0--0
093h PIE3
(1)
— — CCP4IE CCP3IE TMR6IE — TMR4IE — --00 0-0- --00 0-0-
094h PIE4
(1)
— — — — — — BCL2IE SSP2IE ---- --00 ---- --00
095h
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
096h PCON STKOVF STKUNF
— —RMCLRRI POR BOR 00-- 11qq qq-- qquu
097h WDTCON
— — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110
098h OSCTUNE
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000
099h OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0
— SCS1 SCS0 0011 1-00 0011 1-00
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0
— CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS2 ADCS1 ADCS0
— ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000
09Fh
— Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: PIC16(L)F1827 only.