Datasheet

PIC16(L)F1826/27
DS41391D-page 236  2011 Microchip Technology Inc.
25.2.2 SPI MODE OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCKx)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSPx Enable bit, SSPxEN of
the SSPxCON1 register, must be set. To reset or recon-
figure SPI mode, clear the SSPxEN bit, re-initialize the
SSPxCONx registers and then set the SSPxEN bit.
This configures the SDIx, SDOx, SCKx and SSx
pins
as serial port pins. For the pins to behave as the serial
port function, some must have their data direction bits
(in the TRIS register) appropriately programmed as fol-
lows:
• SDIx must have corresponding TRIS bit set
• SDOx must have corresponding TRIS bit cleared
• SCKx (Master mode) must have corresponding
TRIS bit cleared
• SCKx (Slave mode) must have corresponding
TRIS bit set
• SSx
must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
The MSSPx consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to
the SSPxSR until the received data is ready. Once the
8 bits of data have been received, that byte is moved to
the SSPxBUF register. Then, the Buffer Full Detect bit,
BF of the SSPxSTAT register, and the interrupt flag bit,
SSPxIF, are set. This double-buffering of the received
data (SSPxBUF) allows the next byte to start reception
before reading the data that was just received. Any
write to the SSPxBUF register during
transmission/reception of data will be ignored and the
write collision detect bit WCOL of the SSPxCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the
SSPxBUF register to complete successfully.
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the
next byte of data to transfer is written to the SSPxBUF.
The Buffer Full bit, BF of the SSPxSTAT register,
indicates when SSPxBUF has been loaded with the
received data (transmission is complete). When the
SSPxBUF is read, the BF bit is cleared. This data may
be irrelevant if the SPI is only a transmitter. Generally,
the MSSPx interrupt is used to determine when the
transmission/reception has completed. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur.
FIGURE 25-5: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(BUF)
Shift Register
(SSPxSR)
MSb
LSb
SDOx
SDIx
Processor 1
SCKx
SPI Master SSPxM<3:0> = 00xx
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPxSR)
LSb
MSb
SDIx
SDOx
Processor 2
SCKx
SPI Slave SSPxM<3:0> = 010x
Serial Clock
SSx
Slave Select
General I/O
(optional)
= 1010