Information

 2009-2013 Microchip Technology Inc. DS80000485L-page 5
PIC16(L)F1826/1827
5. Module: ADC
5.1 Analog-to-Digital Conversion
An ADC conversion may not complete under these
conditions:
1. When F
OSC is greater than 8 MHz and it is the
clock source used for the ADC converter.
2. The ADC is operating from its dedicated internal
FRC oscillator and the device is not in Sleep
mode (any F
OSC frequency).
When this occurs, the ADC Interrupt Flag (ADIF)
does not get set, the GO/DONE
bit does not get
cleared, and the conversion result does not get
loaded into the ADRESH and ADRESL result
registers.
Work around
Method 1: Select the system clock, FOSC, as
the ADC clock source and reduce
the F
OSC frequency to 8 MHz or
less when performing ADC
conversions.
Method 2: Select the dedicated FRC
oscillator as the ADC conversion
clock source and perform all
conversions with the device in
Sleep.
Method 3: This method is provided if the
application cannot use Sleep
mode and requires continuous
operation at frequencies above 8
MHz. This method requires early
termination of an ADC conver-
sion. Provide a fixed time delay in
software to stop the A-to-D
conversion manually, after all ten
bits are converted, but before the
conversion would complete
automatically. The conversion is
stopped by clearing the GO/
DONE
bit in software. The GO/
DONE
bit must be cleared during
the last ½ T
AD cycle, before the
conversion would have
completed automatically. Refer to
Figure 1 for details.
FIGURE 1: INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE
In Figure 1, 88 instruction cycles (TCY) will be
required to complete the full conversion. Each T
AD
cycle consists of eight TCY periods. A fixed delay is
provided to stop the A/D conversion after 86
instruction cycles and terminate the conversion at
the correct time as shown in the figure above.
FOSC = 32 MHz
TCY = 4/32 MHz = 125 nsec
TAD = 1 µsec, ADCS = FOSC/32
88 TCY
84 TCY
8 TCY
4 TCY
1 TAD
11 TAD
Stop the A/D conversion
between 10.5 and 11 T
AD
cycles.
See the Analog-to-Digital
Conversion T
AD Cycles
figure in the Analog-to-
Digital Converter chapter of
the device data sheet.
}
See the ADC Clock Period (TAD) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter
section of the device data sheet.