Information

 2009-2013 Microchip Technology Inc. DS80000485L-page 3
PIC16(L)F1826/1827
Silicon Errata Issues
1. Module: Data EE Memory
1.1 Data EE Memory Endurance
The typical write/erase endurance of the Data EE
Memory is limited to 10k cycles.
Work around
Use error correction method that stores data in
multiple locations.
Affected Silicon Revisions
2. Module: Program Flash Memory (PFM)
2.1 Program Flash Memory Endurance
The typical write/erase endurance of the PFM is
limited to 1k cycles when V
DD is above 3.0V.
Work around
Use an error correction method that stores data
in multiple locations.
Affected Silicon Revisions
3. Module: Timer1
3.1 Timer1 Gate Toggle Mode with Timer0 as
Gate Source
Timer1 Gate Toggle mode provides unexpected
results when Timer0 overflow is selected as the
Timer1 gate source. We do not recommend using
Timer0 overflow as the Timer1 gate source while in
Timer1 Gate Toggle mode or when Toggle mode is
used in conjunction with Timer1 Gate Single-Pulse
mode.
Work around
None.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A6).
A2 A3 A4 A5 A6
X X
A2 A3 A4 A5 A6
X X
A2 A3 A4 A5 A6
X X