Information

 2009-2013 Microchip Technology Inc. DS80000485L-page 13
PIC16(L)F1826/1827
2. Module: Oscillator
5.5 Fail-Safe Clock Monitor
5.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or changing the
SCS bits of the OSCCON register. When the SCS
bits are changed, the OST is restarted. While the
OST is running, the device continues to operate
from the INTOSC selected in OSCCON. When the
OST times out, the Fail-Safe condition is cleared
after successfully switching to the external
clock source. The OSFIF bit should be cleared
prior to switching to the external clock source.
If the Fail-Safe condition still exists, the OSFIF
flag will again become set by hardware.