Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PDIP 18 8-Bit 32 MHz I/O number 16

 2009-2013 Microchip Technology Inc. DS80000485L-page 1

PIC16(L)F1826/1827

The PIC16(L)F1826/1827 family devices that you have

received conform functionally to the current Device

Data Sheet (DS41391D), except for the anomalies

described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Tab le 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC16(L)F1826/1827 silicon.

Data Sheet clarifications and corrections start on page

12, following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level

using MPLAB IDE in conjunction with a hardware

debugger:

1. Using the appropriate interface, connect the

device to the hardware debugger.

2. Open an MPLAB IDE project.

3. Configure the MPLAB IDE project for the

appropriate device and hardware debugger.

4. Based on the version of MPLAB IDE you are

using, do one of the following:

a) For MPLAB IDE 8, select Programmer >

Reconnect.

b) For MPLAB X IDE, select Window >

Dashboard and click the Refresh Debug

Tool Status icon ( ).

5. Depending on the development tool used, the

part number and Device Revision ID value

appear in the Output window.

The DEVREV values for the various PIC16(L)F1826/

1827 silicon revisions are shown in Table 1 .

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A6).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number

DEVICE ID<13:0>

(1),(2)

DEV<8:0>

Revision ID for Silicon Revision

A2 A3 A4 A5 A6

PIC16F1826 10 0111 100 0 0010 0 0011 0 0100 0 0101 0 0110

PIC16LF1826 10 1000 100 0 0010 0 0011 0 0100 0 0101 0 0110

PIC16F1827 10 0111 101 0 0010 0 0011 0 0100 0 0101 0 0110

PIC16LF1827 10 1000 101 0 0010 0 0011 0 0100 0 0101 0 0110

Note 1: The Device ID is located in the configuration memory at address 8006h.

2: Refer to the “PIC12(L)F1822/PIC16(L)F182X Memory Programming Specification” (DS41390)

for detailed information on Device and Revision IDs for your specific device.

PIC16(L)F1826/1827 Family

Silicon Errata and Data Sheet Clarification

Summary of content (16 pages)

PAGE 1
PIC16(L)F1826/1827 PIC16(L)F1826/1827 Family Silicon Errata and Data Sheet Clarification The PIC16(L)F1826/1827 family devices that you have received conform functionally to the current Device Data Sheet (DS41391D), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1.
PAGE 2
PIC16(L)F1826/1827 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) A2 A3 A4 A5 A6 Data EE Memory Memory Endurance 1.1 Erase/Write endurance limited. X X Program Flash Memory (PFM) Endurance 2.1 Erase/Write endurance limited. X X Timer1 Timer0 Gate Source 3.1 Toggle mode works improperly. X X Oscillator HS mode 4.1 Frequency/Voltage range. X X X X X Oscillator HFINTOSC Ready/ Stable bit 4.
PAGE 3
PIC16(L)F1826/1827 Silicon Errata Issues Note: 3. Module: Timer1 This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A6). 1. Module: Data EE Memory 1.1 Data EE Memory Endurance The typical write/erase endurance of the Data EE Memory is limited to 10k cycles. 3.
PAGE 4
PIC16(L)F1826/1827 4. Module: Oscillator 4.1 HS Oscillator Frequency The Standard Operating Conditions for the HS Oscillator are as follows: Characteristic Min. Typ† Max. Oscillator Frequency 1 — Oscillator Frequency 1 — Units Conditions Operating Temperature 20 MHz HS Oscillator mode, VDD > 2.3V -40°C  TA  +85°C 20 MHz HS Oscillator mode, VDD  2.8V -40°C  TA  +125°C 4.3 Oscillator Start-up Timer (OST) bit Work around None.
PAGE 5
PIC16(L)F1826/1827 5. Module: ADC 5.1 Analog-to-Digital Conversion An ADC conversion may not complete under these conditions: 1. 2. When FOSC is greater than 8 MHz and it is the clock source used for the ADC converter. The ADC is operating from its dedicated internal FRC oscillator and the device is not in Sleep mode (any FOSC frequency).
PAGE 6
PIC16(L)F1826/1827 Note: The exact delay time will depend on the TAD divisor (ADCS) selection. The TCY counts shown in the timing diagram above apply to this example only. Refer to Table 3 for the required delay counts for other configurations.
PAGE 7
PIC16(L)F1826/1827 7. Module: Resets 8. Module: Timer1 7.1 Reset under Low-Power Conditions 8.1 Timer1 Gate Toggle mode This issue pertains only to the F product version, PIC16F1826/1827. The LF product version, PIC16LF1826/1827, is not affected by this issue in any way.
PAGE 8
PIC16(L)F1826/1827 9. Module: BOR Note: 9.1 BOR Reset This issue affects only the PIC16LF1826/1827 devices. The device may undergo a BOR Reset when waking-up from Sleep and BOR is reenabled. A BOR Reset may also occur the moment the software BOR is enabled. Under certain voltage and temperature conditions and when either SBODEN or BOR_NSLEEP is selected, the devices may occasionally Reset when waking-up from Sleep or BOR is enabled.
PAGE 9
PIC16(L)F1826/1827 10. Module: Enhanced Universal Synchronous Asynchronous Receiver (EUSART) 10.1 16-Bit High-Speed Asynchronous Mode The EUSART provides unexpected operation when the 16-Bit High-Speed Asynchronous mode is selected and the Baud Rate Generator Data register values are loaded with zero. We do not recommend using this configuration for EUSART communication.
PAGE 10
PIC16(L)F1826/1827 10.2 Auto-Baud Detect When using automatic baud detection (ABDEN), on occasion, an incorrect count value can be stored at the end of auto-baud detection in the SPBRGH:SPBRGL (SPBRG) registers. The SPBRG value may be off by several counts. This condition happens sporadically when the device clock frequency drifts to a frequency where the SPBRG value oscillates between two different values. The issue is present regardless of the baud rate Configuration bit settings.
PAGE 11
PIC16(L)F1826/1827 EXAMPLE 3: METHOD 2 – EUSART AUTO-BAUD DETECT WORK AROUND Similar to Method 1, define default, minimum and maximum auto-baud (SPBRG) values. In firmware, compute a running average of SPBRG. If the new SPBRG value falls outside the minimum or maximum limits, then use the current running average value (Average_Baud), otherwise use the auto-baud SPBRG value and calculate a new running average.
PAGE 12
PIC16(L)F1826/1827 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41391D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Temperature Indicator In Register 14-1: FVRCON: Fixed Voltage Reference Control Register, the TSEN and TSRNG bits that enable and select the range for the temperature indicator module are missing.
PAGE 13
PIC16(L)F1826/1827 2. Module: Oscillator 5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source.
PAGE 14
PIC16(L)F1826/1827 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (10/2009) Initial release of this document. Rev B Document (02/2010) Added PIC16F1826 and PIC16F1827 to this errata; Added Rev. A3 for PIC16F/LF1826/1827. Data Sheet Clarifications: Added Modules 1 thru 5. Rev C Document (05/2010) Added Modules 5, 6 and 7. Rev D Document (06/2010) Removed Module 6 (Oscillator); Added Modules 7 (Resets) and 8 (Timer1). Data Sheet Clarifications: Removed Modules 1 to 5.
PAGE 15
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 16
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.