Datasheet

PIC16(L)F1826/27
DS41391D-page 90  2011 Microchip Technology Inc.
8.6.5 PIE4 REGISTER
(1)
The PIE4 register contains the interrupt enable bits, as
shown in Register 8-5.
Note 1: The PIE4 register is available only on the
PIC16(L)F1827 device.
2: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 8-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
(1)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — BCL2IE SSP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Unimplemented: Read as ‘0’
bit 1 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1 = Enables the MSSP2 Bus Collision Interrupt
0 = Disables the MSSP2 Bus Collision Interrupt
bit 0 SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit
1 = Enables the MSSP2 interrupt
0 = Disables the MSSP2 interrupt
Note 1: This register is only available on PIC16(L)F1827.