Information

 2011-2013 Microchip Technology Inc. DS80000517E-page 3
PIC16(L)F1825/1829
Silicon Errata Issues
1. Module: Oscillator
1.1 LFINTOSC
The device may not wake-up from Sleep mode
when the LFINTOSC is selected as the system
clock.
Work around
Enable the Fail-Safe Clock Monitor (FSCM)
feature before initiating Sleep mode. When the
Fail-Safe Clock Monitor (FSCM) feature is enabled
before entering Sleep mode, the device will wake
from Sleep.
Affected Silicon Revisions
1.2 OSCSTAT bits: HFIOFR and HFIOFS
When HFINTOSC is selected, the HFIOFR and
HFIOFS bits will become set when the oscillator
becomes ready and stable. Once these bits are
set, they become “stuck”, indicating that
HFINTOSC is always ready and stable. If the
HFINTOSC is disabled, the bits fail to be cleared.
Work around
None.
Affected Silicon Revisions
1.3 Clock Switching
When switching clock sources between INTOSC
clock source and an external clock source, one
corrupted instruction may be executed after the
switch occurs.
This issue does not affect Two-Speed Start-up or
the Fail-Safe Clock Monitor operation.
Work around
When switching from an external oscillator clock
source, first switch to 16 MHz HFINTOSC. Once
running at 16 MHz HFINTOSC, configure IRCF to
run at desired internal oscillator frequency.
When switching from an internal oscillator
(INTOSC) to an external oscillator clock source,
first switch to HFINTOSC High-Power mode
(8 MHz or 16 MHz). Once running from
HFINTOSC, switch to the external oscillator clock
source.
Affected Silicon Revisions
1.4 Oscillator Start-up Timer
During the Two-Speed Start-up sequence, the
Oscillator Start-up Timer is enabled to count 1024
clock cycles. After the count is reached, the OSTS
bit is set, the system clock is held low until the next
falling edge of the external crystal (LP, XT or HS
mode), before switching to the external clock
source.
When an external oscillator is configured as the
primary clock and Fail-Safe Clock mode is enabled
(FCMEN = 1), any of the following conditions will
result in the Oscillator Start-up Timer failing to
restart:
•MCLR
Reset
• Wake from Sleep
• Clock change from INTOSC to Primary Clock
This anomaly will manifest itself as a clock failure
condition for external oscillators which take longer
than the clock failure time-out period to start.
Work around
None.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
A0
A2
X
A0 A2
X
X
A0 A2
X
A0 A2
X
X