Datasheet

PIC16(L)F1824/1828

DS41419D-page 74  2010-2012 Microchip Technology Inc.

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CLKREN: Reference Clock Module Enable bit

1 = Reference Clock module is enabled

0 = Reference Clock module is disabled

bit 6 CLKROE: Reference Clock Output Enable bit

(3)

1 = Reference Clock output is enabled on CLKR pin

0 = Reference Clock output disabled on CLKR pin

bit 5 CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit

1 = Slew Rate limiting is enabled

0 = Slew Rate limiting is disabled

bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits

11 = Clock outputs duty cycle of 75%

10 = Clock outputs duty cycle of 50%

01 = Clock outputs duty cycle of 25%

00 = Clock outputs duty cycle of 0%

bit 2-0 CLKRDIV<2:0> Reference Clock Divider bits

111 = Base clock value divided by 128

110 = Base clock value divided by 64

101 = Base clock value divided by 32

100 = Base clock value divided by 16

011 = Base clock value divided by 8

010 = Base clock value divided by 4

001 = Base clock value divided by 2

(1)

000 = Base clock value

(2)

Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.

2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%

is selected.

3: To route CLKR to pin, CLKOUTEN

of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration

Word 1 = 0 will result in F

OSC/4. See Section 6.3 “Conflicts with the CLKR pin” for details.