Datasheet

PIC16(L)F1824/1828
DS41419D-page 282  2010-2012 Microchip Technology Inc.
FIGURE 25-29: I
2
C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4
A3 A2 A1
SDA SCL
12
3
4
5
6
7
8
9
12
3
4
5
678 9
1234
Bus master terminates
transfer
ACK
Receiving Data from Slave
Receiving Data from Slave
D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSP1IF BF
ACK is not sent
Write to SSP1CON2<0>(SEN = 1),
Write to SSP1BUF occurs here,
ACK from Slave
Master configured as a receiver by programming SSP1CON2<3> (RCEN = 1)
PEN bit = 1 written here
Data shifted in on falling edge of CLK
Cleared by software
start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1 while CPU
(SSP1STAT<0>)
ACK
Cleared by software
Cleared by software
Set SSP1IF interrupt at end of receive
Set P bit (SSP1STAT<4>) and SSP1IF
Cleared in software
ACK from Master
Set SSP1IF at end
Set SSP1IF interrupt at end of Acknowledge sequence
Set SSP1IF interrupt at end of Acknow- ledge sequence
of receive
Set ACKEN, start Acknowledge sequence
SSPOV is set because SSP1BUF is still full
SDA = ACKDT = 1
RCEN cleared automatically
RCEN = 1, start next receive
Write to SSP1CON2<4> to start Acknowledge sequence SDA = ACKDT (SSP1CON2<5>) = 0
RCEN cleared automatically
responds to SSP1IF
ACKEN
begin Start condition
Cleared by software
SDA = ACKDT = 0
Last bit is shifted into SSP1SR and contents are unloaded into SSP1BUF
RCEN
Master configured as a receiver by programming SSP1CON2<3> (RCEN = 1)
RCEN cleared automatically
ACK from Master
SDA\ = ACKDT = 0
RCEN cleared automatically