Datasheet

PIC16(L)F1824/1828
DS41419D-page 244  2010-2012 Microchip Technology Inc.
The I
2
C interface supports the following modes and
features:
•Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
•Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 25-2 is a block diagram of the I
2
C interface
module in Master mode. Figure 25-3 is a diagram of the
I
2
C interface module in Slave mode.
FIGURE 25-2: MSSP1 BLOCK DIAGRAM (I
2
C™ MASTER MODE)
Read Write
SSP1SR
Start bit, Stop bit,
Start bit detect,
SSP1BUF
Internal
data bus
Set/Reset: S, P, SSP1STAT, WCOL, SSPOV
Shift
Clock
MSb
LSb
SDA
Acknowledge
Generate (SSP1CON2)
Stop bit detect
Write collision detect
Clock arbitration
State counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
Receive Enable (RCEN)
Clock Cntl
Clock arbitrate/BCOL detect
(Hold off clock source)
[SSPM 3:0]
Baud rate
Reset SEN, PEN (SSP1CON2)
generator
(SSP1ADD)
Address Match detect
Set SSP1IF, BCL1IF