Datasheet

 2010-2012 Microchip Technology Inc. DS41419D-page 153
PIC16(L)F1824/1828
TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION T
AD CYCLES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
Clock Source
ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Fosc/2 000
62.5ns
(2)
100 ns
(2)
125 ns
(2)
250 ns
(2)
500 ns
(2)
2.0 s
Fosc/4 100
125 ns
(2)
200 ns
(2)
250 ns
(2)
500 ns
(2)
1.0 s4.0 s
Fosc/8 001
0.5 s
(2)
400 ns
(2)
0.5 s
(2)
1.0 s2.0 s 8.0 s
(3)
Fosc/16 101 800 ns 800 ns 1.0 s2.0 s4.0 s 16.0 s
(3)
Fosc/32 010 1.0 s1.6 s2.0 s4.0 s 8.0 s
(3)
32.0 s
(3)
Fosc/64 110 2.0 s3.2 s4.0 s 8.0 s
(3)
16.0 s
(3)
64.0 s
(3)
FRC x11 1.0-6.0 s
(1,4)
1.0-6.0 s
(1,4)
1.0-6.0 s
(1,4)
1.0-6.0 s
(1,4)
1.0-6.0 s
(1,4)
1.0-6.0 s
(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The F
RC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required T
AD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (T
AD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock F
OSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
TAD1 TAD2
TAD3
TAD4 TAD5
TAD6 TAD7
TAD8
TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY - TAD
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
On the following cycle: