PIC16(L)F1824/1828 Data Sheet 14/20-Pin Flash Microcontrollers with XLP Technology 2010-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16(L)F1824/1828 14/20-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU: • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 32 MHz oscillator/clock input - DC – 125 ns instruction cycle • Up to 8 Kbytes Linear Program Memory addressing • Up to 256 bytes Linear Data Memory Addressing • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset • Direct, Indirect and
PIC16(L)F1824/1828 Note: For other small form-factor package availability and marking www.microchip.com/packaging or contact your local sales office.
PIC16(L)F1824/1828 FIGURE 1: 14-PIN DIAGRAM FOR PIC16(L)F1824 PDIP, SOIC, TSSOP 14 VSS RA5 2 RA4 3 13 RA0/ICSPDAT 12 RA1/ICSPCLK 11 RA2 10 RC0 9 RC1 8 RC2 PIC16(L)F1824 VDD 1 MCLR/VPP/RA3 4 RC5 5 RC4 6 RC3 7 FIGURE 2: 16-PIN DIAGRAM FOR PIC16(L)F1824 RA4 13 VSS 14 NC 15 NC RA5 1 16 VDD QFN 12 RA0/ICSPDAT 11 RA1/ICSPCLK 2 MCLR/VPP/RA3 3 PIC16(L)F1824 10 RA2 9 RC0 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 SR Latch Timers ECCP MSSP Interrupt Modulator Pull-up Basic VREFDACOUT CPS0 C1IN+ — — — TX(1) CK(1) — IOC — Y ICSPDAT ICDDAT RA1 12 11 AN1 VREF+ CPS1 C12IN0- SRI — — RX(1) DT(1) — IOC — Y ICSPCLK ICDCLK RA2 11 10 AN2 — CPS2 C1OUT SRQ T0CKI CCP3 FLT0 — — INT/ IOC — Y — RA3 4 3 — — — — — T1G(1) — — SS(1) IOC — Y MCLR VPP RA4 3 2 AN3 — CPS3 — — T1G(1) T1OSO P2B(1) — SDO(1) IOC — Y OSC2 CLKOUT CLKR RA5 2 1 —
PIC16(L)F1824/1828 FIGURE 3: 20-PIN DIAGRAM FOR PIC16(L)F1828 PDIP, SOIC, SSOP VDD FIGURE 4: 20 VSS 2 19 RA0/ICSPDAT RA4 3 18 RA1/ICSPCLK MCLR/VPP/RA3 4 17 RA2 RC5 5 16 RC0 RC4 6 15 RC1 RC3 7 14 RC2 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 PIC16(L)F1828 1 RA5 PIC16(L)F1828 20-PIN QFN 20 RA4 19 RA5 18 VDD 17 Vss 16 ICSPDAT/RA0 QFN 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 Comparator SR Latch Timers CCP EUSART SSP Interrupt Modulator Pull-up Basic 19 16 AN0 VREFDACOUT CPS0 C1IN+ — — — — — IOC — Y ICSPDAT/ ICDDAT RA1 18 15 AN1 VREF+ CPS1 C12IN0- SRI — — — — IOC — Y ICSPCLK/ ICDCLK RA2 17 14 AN2 — CPS2 C1OUT SRQ T0CKI CCP3 FLT0 — — INT/ IOC — Y — RA3 4 1 — — — — T1G(1) — — — IOC — Y(4) MCLR VPP RA4 3 20 AN3 — CPS3 — — T1G(1) T1OSO P2B(1) — — IOC — Y OSC2 CLKOUT CLKR RA5 2
PIC16(L)F1824/1828 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 19 3.0 Memory Organization ............................................................................
PIC16(L)F1824/1828 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC16(L)F1824/1828 1.0 DEVICE OVERVIEW The PIC16(L)F1824/1828 are described within this data sheet. They are available in 14/20 pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1824/1828 devices. Tables 1-2 and 1-3 show the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC16(L)F1824/1828 FIGURE 1-1: PIC16(L)F1824/1828 BLOCK DIAGRAM Program Flash Memory CLKR RAM EEPROM Clock Reference OSC2/CLKOUT Timing Generation OSC1/CLKIN INTRC Oscillator PORTA CPU PORTB(3) (Figure 2-1) MCLR Note 1: 2: 3: DS41419D-page 12 PORTC ADC 10-Bit Timer0 Timer1 Timer2 Timer4 Timer6 Comparators SR Latch ECCP1 ECCP2 CCP3 CCP4 MSSP EUSART See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices.
PIC16(L)F1824/1828 TABLE 1-2: PIC16(L)F1824 PINOUT DESCRIPTION Name RA0/AN0/CPS0/C1IN+/VREF-/ DACOUT/TX(1)/CK(1)/ ICSPDAT/ICDDAT RA1/AN1/CPS1/C12IN0-/VREF+/ SRI/RX(1)/DT(1)/ICSPCLK/ ICDCLK RA2/AN2/CPS2/T0CKI/INT/ C1OUT/SRQ/CCP3/FLT0 RA3/SS(1)/T1G(1)/VPP/MCLR Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. — A/D Channel 0 input. CPS0 AN — Capacitive sensing input 0. C1IN+ AN — Comparator C1 positive input.
PIC16(L)F1824/1828 TABLE 1-2: PIC16(L)F1824 PINOUT DESCRIPTION (CONTINUED) Name RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/CLKR/ SDO(1)/P2B(1)/T1G(1,2) RA5/CLKIN/OSC1/T1OSI/ T1CKI/P2A(1)/CCP2(1) RC0/AN4/CPS4/C2IN+/SCL/ SCK/P1D(1) RC1/AN5/CPS5/C12IN1-/SDA/ SDI/P1C(1)/CCP4 RC2/AN6/CPS6/C12IN2-/ P1D(1,2)/P2B(1,2)/SDO(1,2)/ MDCIN1 Function Input Type RA4 TTL Output Type Description CMOS General purpose I/O. AN3 AN — A/D Channel 3 input. CPS3 AN — Capacitive sensing input 3.
PIC16(L)F1824/1828 TABLE 1-2: PIC16(L)F1824 PINOUT DESCRIPTION (CONTINUED) Name RC3/AN7/CPS7/C12IN3-/ P2A(1,2)/CCP2(1,2)/P1C(1,2)/ SS(1,2)/MDMIN RC4/C2OUT/SRNQ/P1B/TX(1,2)/ CK(1,2)/MDOUT RC5/P1A/CCP1/RX(1,2)/DT(1,2)/ MDCIN2 Function Input Type RC3 TTL Output Type Description CMOS General purpose I/O. AN7 AN — CPS7 AN — A/D Channel 7 input. Capacitive sensing input 7. C12IN3- AN — Comparator C1 or C2 negative input. P2A — CMOS PWM output. CCP2 ST CMOS Capture/Compare/PWM2.
PIC16(L)F1824/1828 TABLE 1-3: PIC16(L)F1828 PINOUT DESCRIPTION Name RA0/AN0/CPS0/C1IN+/VREF-/ DACOUT/ICSPDAT/ICDDAT RA1/AN1/CPS1/C12IN0-/VREF+/ SRI/ICSPCLK/ICDCLK RA2/AN2/CPS2/T0CKI/INT/ C1OUT/SRQ/CCP3/FLT0 RA3/T1G(1)/VPP/MCLR RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/CLKR/P2B(1)/ T1G(1,2) Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. — A/D Channel 0 input. CPS0 AN — Capacitive sensing input 0. C1IN+ AN — Comparator C1 positive input.
PIC16(L)F1824/1828 TABLE 1-3: PIC16(L)F1828 PINOUT DESCRIPTION (CONTINUED) Name RA5/CLKIN/OSC1/T1OSI/ T1CKI/P2A(1)/CCP2(1) RB4/AN10/CPS10/SDA1/SDI1 RB5/AN11/CPS11/RX(1,2)/DT(1,2) RB6/SCL1/SCK1 RB7/TX(1,2)/CK(1,2) RC0/AN4/CPS4/C2IN+/P1D(1) RC1/AN5/CPS5/C12IN1-/P1C(1) RC2/AN6/CPS6/C12IN2-/ P1D(1,2)/P2B(1,2)/MDCIN1 Function Input Type Output Type RA5 TTL CLKIN CMOS — OSC1 XTAL — T1OSI XTAL XTAL T1CKI ST — Description CMOS General purpose I/O. External clock input (EC mode).
PIC16(L)F1824/1828 TABLE 1-3: PIC16(L)F1828 PINOUT DESCRIPTION (CONTINUED) Name RC3/AN7/CPS7/C12IN3-/ P2A(1,2)/CCP2(1,2)/P1C(1,2)/ MDMIN RC4/C2OUT/SRNQ/P1B/TX(1)/ CK(1)/MDOUT RC5/P1A/CCP1/RX(1)/DT(1)/ MDCIN2 RC6/AN8/CPS8/CCP4/SS RC7/AN9/CPS9/SDO Function Input Type RC3 TTL Output Type Description CMOS General purpose I/O. AN7 AN — CPS7 AN — Capacitive sensing input 7. C12IN3- AN — Comparator C1 or C2 negative input. P2A — CCP2 AN P1C — MDMIN — RC4 TTL A/D Channel 7 input.
PIC16(L)F1824/1828 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC16(L)F1824/1828 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscilla
PIC16(L)F1824/1828 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM • Data EEPROM memory(1) The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.
PIC16(L)F1824/1828 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1824/1828 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 RETLW Instruction Stack Level 0 Stack Level 1 The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
PIC16(L)F1824/1828 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete.
PIC16(L)F1824/1828 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16(L)F1824/1828 3.2.2 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.
PIC16F1824/PIC16F1828 MEMORY MAP, BANKS 0-7 BANK 0 2010-2012 Microchip Technology Inc.
2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 MEMORY MAP, BANKS 16-23 BANK 16 2010-2012 Microchip Technology Inc.
2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 TABLE 3-8: PIC16(L)F1824/1828 MEMORY MAP, BANK 31 Bank 31 FA0h Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC16(L)F1824 PIC16(L)F1828 Bank(s) Page No.
PIC16(L)F1824/1828 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 000h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h(1) PCL Program Counter (PC) Least S
PIC16(L)F1824/1828 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 1 080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 082h(1) PCL Program Counter
PIC16(L)F1824/1828 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 102h(1) PCL Program Counter
PIC16(L)F1824/1828 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 182h(1) PCL Program Counter
PIC16(L)F1824/1828 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 202h(1) PCL Program Counter
PIC16(L)F1824/1828 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 5 280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 282h(1) PCL Program Counter
PIC16(L)F1824/1828 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 6 300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 302h(1) PCL Program Counter
PIC16(L)F1824/1828 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 382h(1) PCL Program Counter
PIC16(L)F1824/1828 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 8 400h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 401h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 402h(1) PCL Program Counter
PIC16(L)F1824/1828 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Banks 9-30 x00h/ x80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(1)
PIC16(L)F1824/1828 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 31 F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(1) PCL Program Counter
PIC16(L)F1824/1828 3.3 3.3.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC.
PIC16(L)F1824/1828 3.4 3.4.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow.
PIC16(L)F1824/1828 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC16(L)F1824/1828 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.
PIC16(L)F1824/1828 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41419D-page 46 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC16(L)F1824/1828 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC16(L)F1824/1828 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and programmers.
PIC16(L)F1824/1828 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 R/P-1/1 R/P-1/1 FCMEN IESO CLKOUTEN R/P-1/1 R/P-1/1 BOREN<1:0> bit 13 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE R/P-1/1 CPD bit 8 R/P-1/1 R/P-1/1 WDTE<1:0> R/P-1/1 R/P-1/1 R/P-1/1 FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail
PIC16(L)F1824/1828 REGISTER 4-1: bit 2-0 Note 1: 2: 3: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.
PIC16(L)F1824/1828 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1/1 R/P-1/1 U-1 R/P-1/1 R/P-1/1 R/P-1/1 LVP(1) DEBUG(2) — BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 U-1 R-1 U-1 U-1 — — — Reserved — — R/P-1/1 bit 7 R/P-1/1 WRT<1:0> bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase Legend: bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming
PIC16(L)F1824/1828 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1.
PIC16(L)F1824/1828 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.
PIC16(L)F1824/1828 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC16(L)F1824/1828 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Oscillator Timer1 FOSC<2:0> = 100 T1OSO IRCF<3:0> HFPLL 500 kHz Source 16 MHz (HFINTOSC) Postscaler Internal Oscillator Block 500 kHz (MFINTOSC) 31 kHz Source 31 kHz 31 kHz (LFINTOSC) DS41419D-page 56 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.
PIC16(L)F1824/1828 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained internally within the oscillator module.
PIC16(L)F1824/1828 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 To Internal Logic Quartz Crystal C2 Note 1: 2: OSC1/CLKIN RS(1) RF(2) C1 Sleep OSC2/CLKOUT A series resistor (RS) may be required for quartz crystals with low drive level. RP(3) C2 Ceramic RS(1) Resonator Note 1: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
PIC16(L)F1824/1828 5.2.1.4 4xPLL The oscillator module contains a 4xPLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4xPLL must fall within specifications. See the PLL Clock Timing Specifications in Section 30.0 “Electrical Specifications”. The 4xPLL may be enabled for use by one of two methods: 1. 2. Program the PLLEN bit in Configuration Word 2 to a ‘1’. Write the SPLLEN bit in the OSCCON register to a ‘1’.
PIC16(L)F1824/1828 5.2.1.6 External RC Mode 5.2.2 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1.
PIC16(L)F1824/1828 5.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.
PIC16(L)F1824/1828 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The outputs of the 16 MHz HFINTOSC postscaler and the LFINTOSC connect to a multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators.
PIC16(L)F1824/1828 5.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators.
PIC16(L)F1824/1828 FIGURE 5-7: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFIN
PIC16(L)F1824/1828 5.3 Clock Switching 5.3.3 TIMER1 OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins.
PIC16(L)F1824/1828 5.4 5.4.1 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC16(L)F1824/1828 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
PIC16(L)F1824/1828 5.5 5.5.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word 1. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC).
PIC16(L)F1824/1828 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 5.
PIC16(L)F1824/1828 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscilla
PIC16(L)F1824/1828 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<4:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = • • • 000001 = 0
PIC16(L)F1824/1828 6.0 REFERENCE CLOCK MODULE 6.3 Conflicts with the CLKR pin The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR) and provide a secondary internal clock source to the modulator module. This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application.
PIC16(L)F1824/1828 REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 CLKREN CLKROE CLKRSLR R/W-1/1 R/W-0/0 R/W-0/0 CLKRDC<1:0> R/W-0/0 R/W-0/0 CLKRDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 = Reference Clock module is e
PIC16(L)F1824/1828 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Name CLKRCON Legend: Bit 7 Bit 6 Bit 5 CLKREN CLKROE CLKRSLR CONFIG1 Legend: Bit 3 CLKRDC<1:0> Bit 2 Bit 1 Bit 0 CLKRDIV<2:0> Register on Page 74 — = unimplemented locations, read as ‘0’. Shaded cells are not used by reference clock sources.
PIC16(L)F1824/1828 NOTES: DS41419D-page 76 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 7.0 RESETS There are multiple ways to reset this device: • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 7-1.
PIC16(L)F1824/1828 7.1 Power-on Reset (POR) 7.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16(L)F1824/1828 FIGURE 7-2: BROWN-OUT READY SBOREN TBORRDY BORRDY FIGURE 7-3: BOR Protection Active BROWN-OUT SITUATIONS VDD Internal Reset VBOR TPWRT(1) VDD Internal Reset VBOR < TPWRT TPWRT(1) VDD Internal Reset Note 1: VBOR TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’. 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 REGISTER 7-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN — — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Word 1 0
PIC16(L)F1824/1828 7.3 MCLR 7.7 The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Word 1 and the LVP bit of Configuration Word 2 (Table 7-2). TABLE 7-2: MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 7.3.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up.
PIC16(L)F1824/1828 FIGURE 7-4: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC DS41419D-page 82 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 7.10 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 7-3 and Table 7-4 show the Reset conditions of these registers.
PIC16(L)F1824/1828 7.11 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUNF) MCLR Reset (RMCLR) The PCON register bits are shown in Register 7-2.
PIC16(L)F1824/1828 TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN — — — — — — BORRDY 80 PCON STKOVF STKUNF — — RMCLR RI POR BOR 84 STATUS — — — TO PD Z DC C 24 WDTCON — — SWDTEN 105 WDTPS<4:0> Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
PIC16(L)F1824/1828 NOTES: DS41419D-page 86 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC16(L)F1824/1828 FIGURE 8-2: PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF To Interrupt Logic (Figure 8-1) TMR1IE TMR6IF TMR6IE EEIF EEIE OSFIF OSFIE C1IF C1IE C2IF C2IE BCL1IF BCL1IE Note 1: DS41419D-page 88 PIC16(L)F1828 only. 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 8.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register) 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins.
PIC16(L)F1824/1828 FIGURE 8-3: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NO
PIC16(L)F1824/1828 FIGURE 8-4: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Dummy Cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1).
PIC16(L)F1824/1828 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F1824/1828 8.5.1 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 8-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register.
PIC16(L)F1824/1828 8.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 8-2. REGISTER 8-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F1824/1828 8.5.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 8-3. REGISTER 8-3: R/W-0/0 Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F1824/1828 8.5.4 PIE3 REGISTER The PIE3 register contains the interrupt enable bits, as shown in Register 8-4. REGISTER 8-4: Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F1824/1828 8.5.5 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 8-5. REGISTER 8-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F1824/1828 8.5.6 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 8-6. REGISTER 8-6: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F1824/1828 8.5.7 PIR3 REGISTER The PIR3 register contains the interrupt flag bits, as shown in Register 8-7. REGISTER 8-7: Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F1824/1828 TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 187 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 95 OPTION_REG PIE3 — — CCP4IE CCP3IE TMR6IE — TMR4IE — 96 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF
PIC16(L)F1824/1828 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. WDT will be cleared but keeps running, if enabled for operation during Sleep. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5.
PIC16(L)F1824/1828 Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.
PIC16(L)F1824/1828 10.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC16(L)F1824/1828 10.1 Independent Clock Source 10.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. 10.2 Time-Out Period The WDTPS bits of the WDTCON register set the time-out period from 1ms to 256 seconds. After a Reset, the default time-out period is 2 seconds. WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word 1. See Table 10-1. 10.2.
PIC16(L)F1824/1828 REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select
PIC16(L)F1824/1828 NOTES: DS41419D-page 106 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 11.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL The data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs).
PIC16(L)F1824/1828 11.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 30.
PIC16(L)F1824/1828 Required Sequence EXAMPLE 11-2: DATA EEPROM WRITE BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BTFSC GOTO INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, $-2 ;Disable INTs.
PIC16(L)F1824/1828 11.3 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software.
PIC16(L)F1824/1828 EXAMPLE 11-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF BCF BSF NOP NOP BSF EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; ; Do n
PIC16(L)F1824/1828 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH:EEADRL register pair with the address of the new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD, FREE and WREN bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the erase operation.
PIC16(L)F1824/1828 After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode, as the clocks and peripherals will FIGURE 11-2: continue to run. The processor does not stall when LWLO = 1, loading the write latches.
PIC16(L)F1824/1828 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2.
PIC16(L)F1824/1828 EXAMPLE 11-5: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL 4.
PIC16(L)F1824/1828 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. 8. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16(L)F1824/1828 11.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 11-6) to the desired value to be written. Example 11-6 shows how to verify a write to EEPROM.
PIC16(L)F1824/1828 REGISTER 11-1: R/W-x/u EEDATL: EEPROM DATA REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM
PIC16(L)F1824/1828 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory S
PIC16(L)F1824/1828 REGISTER 11-6: W-0/0 EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the W
PIC16(L)F1824/1828 12.0 I/O PORTS 12.1 Depending on the device selected and peripherals enabled, there are up to two ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC16(L)F1824/1828 REGISTER 12-1: APFCON0: ALTERNATE PIN FUNCTION CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 RXDTSEL SDOSEL(1) SSSEL(1) — T1GSEL TXCKSEL — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RXDTSEL: Pin Selection (PIC16(L)F1824) 0 = RX/DT function is on RC5 1 =
PIC16(L)F1824/1828 REGISTER 12-2: APFCON1: ALTERNATE PIN FUNCTION CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — P1DSEL P1CSEL P2BSEL CCP2SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 P1DSEL: Pin Selection 0 = P1D function is on RC2
PIC16(L)F1824/1828 12.2 PORTA Registers PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-4). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as ‘1’.
PIC16(L)F1824/1828 12.2.3 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists.
PIC16(L)F1824/1828 REGISTER 12-3: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL No
PIC16(L)F1824/1828 REGISTER 12-5: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemen
PIC16(L)F1824/1828 REGISTER 12-7: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits 1 = Pull-up ena
PIC16(L)F1824/1828 TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 127 RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL — — 122 APFCON1 — — — — P1DSEL P1CSEL P2BSEL CCP2SEL 123 INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128 LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 127 RA0 126 Name ANSELA APFCON0(1) WPUEN INTEDG TMR0CS TMR0SE PSA PORTA
PIC16(L)F1824/1828 12.3 PORTB Registers (PIC16(L)F1828 only) PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-10). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1824/1828 12.3.3 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input and some digital input functions are not included in the list below.
PIC16(L)F1824/1828 REGISTER 12-9: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 RB<7:4>: PORTB General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3-0 Unimplemented: Read as ‘0’
PIC16(L)F1824/1828 REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 ANSB7 ANSB6 ANSB5 ANSB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 ANSB<7:4>: Analog Select between Analog or Digital Function on pins RB<7:4>, respectively 0 = Digital I/
PIC16(L)F1824/1828 TABLE 12-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB ANSB7 ANSB6 ANSB5 ANSB4 — — — — 133 INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 133 LATB7 LATB6 LATB5 LATB4 — — — — 132 LATB PORTB RB7 RB6 RB5 RB4 — — — — 132 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 132 WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 133 Legend: Note 1: x = unknown, u = unchan
PIC16(L)F1824/1828 12.4 PORTC Registers PORTC is a 6-bit wide (8-bit wide for PIC16(L)F1828), bidirectional port. The corresponding data direction register is TRISC (Register 12-16). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1824/1828 12.4.3 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input and some digital input functions are not included in the list below.
PIC16(L)F1824/1828 REGISTER 12-15: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RC<7:0>: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1
PIC16(L)F1824/1828 REGISTER 12-18: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSC7(1) ANSC6(1) — — ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively(1)
PIC16(L)F1824/1828 REGISTER 12-20: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER U-0(3) R/W-1/1(2) U-0(3) R/W-1/1(2) R/W-0/0(3) R/W-1/1(2) R/W-0/0(3) R/W-1/1(2) R/W-0/0(3) R/W-1/1(2) R/W-0/0(3) R/W-1/1(2) R/W-0/0(3) R/W-1/1(2) R/W-0/0(3) R/W-1/1(2) INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all oth
PIC16(L)F1824/1828 NOTES: DS41419D-page 140 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 13.0 INTERRUPT-ON-CHANGE The PORTA pins can be configured to operate as Interrupt-on-Change (IOC) pins. On the PIC16(L)F1828 devices, the PORTB pins can also be configured to operate as IOC pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt.
PIC16(L)F1824/1828 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCIE IOCANx D Q IOCAFx From all other IOCAFx individual pin detectors CK R IOC Interrupt to CPU Core RAx IOCAPx D Q CK R Q2 Clock Cycle DS41419D-page 142 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP<5:0>: Interrupt-on-
PIC16(L)F1824/1828 REGISTER 13-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER (PIC16(L)F1828 ONLY) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable
PIC16(L)F1824/1828 REGISTER 13-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER (PIC16(L)F1828 ONLY) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-4 IOCBF<7:4>: Interrupt-on-Change PORTB F
PIC16(L)F1824/1828 NOTES: DS41419D-page 146 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 14.0 FIXED VOLTAGE REFERENCE (FVR) 14.1 Independent Gain Amplifiers The Fixed Voltage Reference (FVR), is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers.
PIC16(L)F1824/1828 REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG R/W-0/0 R/W-0/0 R/W-0/0 CDAFVR<1:0> R/W-0/0 ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference
PIC16(L)F1824/1828 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between of -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16(L)F1824/1828 NOTES: DS41419D-page 150 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 16.0 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16(L)F1824/1828 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.
PIC16(L)F1824/1828 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 125 ns (2) (2) (2) (2) Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) Fosc/16 101 800 ns 800 ns 010 1.0 s Fosc/64 110 FRC x11 Fosc/32 Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.
PIC16(L)F1824/1828 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC16(L)F1824/1828 16.2 16.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 “A/D Conversion Procedure”.
PIC16(L)F1824/1828 16.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F1824/1828 16.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC16(L)F1824/1828 REGISTER 16-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 R/W-0/0 — ADNREF R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified.
PIC16(L)F1824/1828 REGISTER 16-3: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-4: R/W-x
PIC16(L)F1824/1828 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC16(L)F1824/1828 16.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4.
PIC16(L)F1824/1828 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC16(L)F1824/1828 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 ADCON0 — CHS4 ADCON1 ADFM A/D Result Register High ADRESL A/D Result Register Low ANSELA ANSELB(1) ANSELC INLVLA INLVLB(1) INLVLC Bit 1 Bit 0 Register on Page CHS1 CHS0 GO/DONE ADON 157 — ADNREF Bit 4 Bit 3 CHS3 CHS2 ADCS<2:0> ADRESH Bit 2 Bit 5 ADPREF<1:0> 158 159, 154 159, 154 — — — ANSA4 — ANSA2 ANSA1 ANSA0 ANSB7 ANSB6 ANSB5 ANSB4 — — — — 133 ANSC7(1) ANSC6(1) — — A
PIC16(L)F1824/1828 NOTES: DS41419D-page 164 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 17.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: • External VREF pins • VDD supply voltage • FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: 17.
PIC16(L)F1824/1828 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSRC+ VDD VREF+ R R 2 R DACEN DACLPS R R 32 Steps R 32-to-1 MUX DACPSS<1:0> DACR<4:0> 5 DAC_output R DACOUT R DACNSS (to Comparator, CSM and ADC modules) DACOE 1 VREF- VSRC- VSS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS41419D-page 166 DACOUT + – Buffered DAC Output 2010-2012 Microchip Tech
PIC16(L)F1824/1828 17.4 Low-Power Voltage State In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSRC+), or the negative voltage source, (VSRC-) can be disabled. The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source. 17.4.
PIC16(L)F1824/1828 REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 DACEN DACLPS DACOE — R/W-0/0 R/W-0/0 U-0 U-0 — DACNSS DACPSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 DACLPS: DAC Lo
PIC16(L)F1824/1828 TABLE 17-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Bit 7 Bit 6 Bit 5 Bit 4 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> DACCON1 — — — Legend: Bit 3 Bit 2 DACR<4:0> Bit 1 Bit 0 ADFVR<1:0> — DACNSS Register on page 148 168 168 — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module. 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 NOTES: DS41419D-page 170 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 18.0 SR LATCH The module consists of a single SR latch with multiple Set and Reset inputs as well as separate latch outputs. The SR latch module includes the following features: • • • • Programmable input selection SR latch output is available externally Separate Q and Q outputs Firmware Set and Reset The SR latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications. 18.
PIC16(L)F1824/1828 FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRPS Pulse Gen(2) SRLEN SRQEN SRI S SRSPE SRCLK Q SRQ SRSCKE SYNCC2OUT(3) SRSC2E SYNCC1OUT(3) SRSC1E SRPR SR Latch(1) Pulse Gen(2) SRI SRRPE SRCLK SRRCKE SYNCC2OUT(3) SRRC2E R Q SRNQ SRLEN SRNQEN SYNCC1OUT(3) SRRC1E Note 1: 2: 3: DS41419D-page 172 If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 Pulse generator causes a 1 Q-state pulse width. Name denotes the connection point at the comparator output.
PIC16(L)F1824/1828 TABLE 18-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 110 256 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz 101 100 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz 011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz 010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz 001 8 4 MHz 2.
PIC16(L)F1824/1828 REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SR latch is set when t
PIC16(L)F1824/1828 TABLE 18-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 127 INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128 INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139 SRQEN SRNQEN SRPS SRPR 173 173 SRCON0 SRLEN SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E TRISA —
PIC16(L)F1824/1828 NOTES: DS41419D-page 176 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 19.0 COMPARATOR MODULE FIGURE 19-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC16(L)F1824/1828 19.2 Comparator Control Each comparator has 2 control registers: CMxCON0 and CMxCON1.
PIC16(L)F1824/1828 19.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. See Section 30.0 “Electrical Specifications” for more information. 19.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 21.
PIC16(L)F1824/1828 19.7 Comparator Negative Input Selection The CxNCH<1:0> bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input. Note: 19.8 To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
PIC16(L)F1824/1828 FIGURE 19-3: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS VA = Analog Voltage = Threshold Voltage VT Note 1: See Section 30.0 “Electrical Specifications”. 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled and consumes no active pow
PIC16(L)F1824/1828 REGISTER 19-2: CMxCON1: COMPARATOR CX CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 U-0 — — R/W-0/0 R/W-0/0 CxNCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt
PIC16(L)F1824/1828 TABLE 19-2: Name CM1CON0 SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page C1ON C1OUT C1OE C1POL --- C1SP C1HYS C1SYNC 182 C2OE C2POL C2HYS C2SYNC CM2CON0 C2ON C2OUT CM1CON1 C1NTP C1INTN CM2CON1 C2NTP C2INTN — — — — DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> DACCON1 — — — FVREN FVRRDY TSEN CMOUT FVRCON — C2SP C1PCH<1:0> — — C2PCH<1:0> — — — — 183 C2NCH<1:0> 18
PIC16(L)F1824/1828 20.0 20.1.2 TIMER0 MODULE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal.
PIC16(L)F1824/1828 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16(L)F1824/1828 20.
PIC16(L)F1824/1828 TABLE 20-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 CPSCON0 CPSON CPSRM — — FVRCON TSEN TSRNG FVREN FVRRDY INLVLA — — INTCON GIE PEIE OPTION_REG WPUEN TMR0 INLVLA5 INLVLA4 TMR0IE INTE INTEDG TMR0CS TMR0SE Bit 3 Bit 2 CPSRNG<1:0> CDAFVR<1:0> INLVLA3 INLVLA2 IOCIE TMR0IF PSA Bit 1 Bit 0 Register on Page CPSOUT T0XCS 333 ADFVR<1:0> 148 INLVLA1 INLVLA0 128 INTF IOCIF PS<2:0> 187 Timer0 Module Register TRISA — —
PIC16(L)F1824/1828 21.0 • • • • TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: Figure 21-1 is a block diagram of the Timer1 module.
PIC16(L)F1824/1828 21.1 Timer1 Operation 21.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 21-2 displays the clock source selections. 21.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle.
PIC16(L)F1824/1828 21.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 21.6 Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable.
PIC16(L)F1824/1828 21.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 21.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 21.6.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1 gate control.
PIC16(L)F1824/1828 21.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
PIC16(L)F1824/1828 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41419D-page 194 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF DS41419D-page 196 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL N+4 Cleared by software 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 21.
PIC16(L)F1824/1828 REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit
PIC16(L)F1824/1828 TABLE 21-5: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 127 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> CCP2CON P2M<:0>1 DC2B<1:0> CCP2M<3:0> INLVLA INTCON PIE1 PIR1 — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 238 INLVLA0 128 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94 TMR1GIF ADIF R
PIC16(L)F1824/1828 NOTES: DS41419D-page 200 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 22.0 TIMER2/4/6 MODULES There are up to three identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). Note: The ‘x’ variable used in this section is used to designate Timer2, Timer4, or Timer6. For example, TxCON references T2CON, T4CON, or T6CON. PRx references PR2, PR4, or PR6.
PIC16(L)F1824/1828 22.1 Timer2/4/6 Operation The clock input to the Timer2/4/6 modules is the system instruction clock (FOSC/4). TMRx increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS<1:0> of the TxCON register. The value of TMRx is compared to that of the Period register, PRx, on each clock cycle.
PIC16(L)F1824/1828 22.
PIC16(L)F1824/1828 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94 PIE3 — — CCP4IE CCP3IE TMR6IE — TMR4IE — 96 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97 PIR3 — — CCP4IF CCP3IF TMR6IF — TMR4IF — 99 PR2 Timer2 Module Period Register 201*
PIC16(L)F1824/1828 23.0 Using this method, the DSM can generate the following types of key modulation schemes: DATA SIGNAL MODULATOR The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output.
PIC16(L)F1824/1828 23.1 DSM Operation The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register, disables the DSM module by automatically switching the carrier high and carrier low signals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current.
PIC16(L)F1824/1828 FIGURE 23-2: ON OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 EXAMPLE 23-1: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State FIGURE 23-3: CARH CARL CARH CARL CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH
PIC16(L)F1824/1828 FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State FIGURE 23-5: CARH CARL CARH CARL FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Falling edges used to sync Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State DS41419D-page 208 CARH CARL CARH CARL 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 23.5 Carrier Source Polarity Select The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL register. 23.
PIC16(L)F1824/1828 REGISTER 23-1: MDCON: MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R-0/0 U-0 U-0 R/W-0/0 MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 =
PIC16(L)F1824/1828 REGISTER 23-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-x/u U-0 U-0 U-0 MDMSODIS — — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDMS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDMSODIS: Modulation Source Output Disable 1 = Output signal driving the peripheral output pin (selected b
PIC16(L)F1824/1828 REGISTER 23-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 MDCHODIS MDCHPOL MDCHSYNC — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCHODIS: Modulator High Carrier Output Disable 1 = Output signal driving the
PIC16(L)F1824/1828 REGISTER 23-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 MDCLODIS MDCLPOL MDCLSYNC — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving th
PIC16(L)F1824/1828 NOTES: DS41419D-page 214 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 24.0 CAPTURE/COMPARE/PWM MODULES Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules.
PIC16(L)F1824/1828 24.1 24.1.2 Capture Mode The Capture mode function described in this section is available and identical for CCP modules ECCP1, ECCP2, CCP3 and CCP4. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively.
PIC16(L)F1824/1828 24.1.5 CAPTURE DURING SLEEP 24.1.6 Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1.
PIC16(L)F1824/1828 24.2 24.2.2 Compare Mode The Compare mode function described in this section is available and identical for CCP modules ECCP1, ECCP2, CCP3 and CCP4. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair.
PIC16(L)F1824/1828 24.2.5 COMPARE DURING SLEEP 24.2.6 The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. TABLE 24-4: Name APFCON1 CCPxCON ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1.
PIC16(L)F1824/1828 24.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
PIC16(L)F1824/1828 24.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCPx pin output driver by setting the associated TRIS bit. Load the PRx register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value.
PIC16(L)F1824/1828 24.3.6 PWM RESOLUTION EQUATION 24-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PRx is 255. The resolution is a function of the PRx register value as shown by Equation 24-4.
PIC16(L)F1824/1828 24.3.7 OPERATION IN SLEEP MODE 24.3.10 In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 24.3.
PIC16(L)F1824/1828 24.4 To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured appropriately. PWM (Enhanced Mode) The enhanced PWM function described in this section is available for CCP modules ECCP1, ECCP2 and ECCP3, with any differences between modules noted. The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD.
PIC16(L)F1824/1828 TABLE 24-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: PWM Steering enables outputs in Single mode.
PIC16(L)F1824/1828 FIGURE 24-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal PRx+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay Delay PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPx
PIC16(L)F1824/1828 24.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 249). This mode can be used for Half-Bridge applications, as shown in Figure 24-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.
PIC16(L)F1824/1828 24.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 24-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure 24-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure 24-11.
PIC16(L)F1824/1828 FIGURE 24-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high. 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 24.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register.
PIC16(L)F1824/1828 FIGURE 24-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: T = TOFF – TON All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver. 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 24.4.3 ENHANCED PWM AUTOSHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist.
PIC16(L)F1824/1828 24.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register. FIGURE 24-15: If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCPxASE bit will be cleared via hardware and normal operation will resume.
PIC16(L)F1824/1828 24.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 24-16: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC16(L)F1824/1828 24.4.6 PWM STEERING MODE In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM<3:2> = 11 and PxM<1:0> = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STRx bits of the PSTRxCON register, as shown in Table 24-9.
PIC16(L)F1824/1828 24.4.6.1 Steering Synchronization The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the Px pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.
PIC16(L)F1824/1828 TABLE 24-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM Name APFCON1 CCPxCON CCPxAS Bit 7 — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — P1DSEL P1CSEL P2BSEL CCP2SEL 123 (1) PxM<1:0> CCPxAS<2:0> CCPTMRS0 C4TSEL<1:0> INLVLA — INLVLC DCxB<1:0> CCPxASE C3TSEL<1:0> — INLVLC7 (1) C2TSEL<1:0> 238 PSSxBD<1:0> 240 C1TSEL<1:0> 239 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1
PIC16(L)F1824/1828 REGISTER 24-1: R/W-00 CCPxCON: CCPx CONTROL REGISTER R/W-0/0 R/W-0/0 PxM<1:0>(1) R/W-0/0 R/W-0/0 DCxB<1:0> R/W-0/0 R/W-0/0 R/W-0/0 CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits(1) Capture mode: Unused Compare mode: Unused If CCP
PIC16(L)F1824/1828 REGISTER 24-2: R/W-0/0 CCPTMRS0: PWM TIMER SELECTION CONTROL REGISTER R/W-0/0 R/W-0/0 C4TSEL<1:0> R/W-0/0 R/W-0/0 C3TSEL<1:0> R/W-0/0 R/W-0/0 C2TSEL<1:0> bit 7 R/W-0/0 C1TSEL<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection bits 00 = CCP4 is based off Timer
PIC16(L)F1824/1828 REGISTER 24-3: R/W-0/0 CCPxAS: CCPx AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 CCPxASE R/W-0/0 R/W-0/0 CCPxAS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 PSSxAC<1:0> R/W-0/0 PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occur
PIC16(L)F1824/1828 REGISTER 24-4: R/W-0/0 PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 PxRSEN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxDC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown
PIC16(L)F1824/1828 PSTRxCON: PWM STEERING CONTROL REGISTER(1) REGISTER 24-5: U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering upda
PIC16(L)F1824/1828 25.0 MASTER SYNCHRONOUS SERIAL PORT MODULE 25.1 Master SSP (MSSP1) Module Overview The Master Synchronous Serial Port (MSSP1) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16(L)F1824/1828 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 25-2 is a block diagram of the I2C interface module in Master mode.
PIC16(L)F1824/1828 FIGURE 25-3: MSSP1 BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSP1BUF Reg SCL Shift Clock SSP1SR Reg SDA MSb LSb SSP1MSK Reg Match Detect Addr Match SSP1ADD Reg Start and Stop bit Detect 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 25.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select.
PIC16(L)F1824/1828 FIGURE 25-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 25.2.1 SPI MODE REGISTERS The MSSP1 module has five registers for SPI mode operation.
PIC16(L)F1824/1828 25.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSP1CON1<5:0> and SSP1STAT<7:6>).
PIC16(L)F1824/1828 FIGURE 25-5: SPI MASTER/SLAVE CONNECTION SPI Master SSP1M<3:0> = 00xx = 1010 SPI Slave SSP1M<3:0> = 010x SDI SDO Serial Input Buffer (BUF) LSb SCK General I/O Processor 1 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 25.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 25-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSP1BUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC16(L)F1824/1828 25.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSP1IF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSP1CON1 register.
PIC16(L)F1824/1828 FIGURE 25-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 25-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Shift register SSP1SR and bit count are reset SSP1BUF to SSP1SR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF DS41419D-page 252
PIC16(L)F1824/1828 FIGURE 25-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active FIGURE 25-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
PIC16(L)F1824/1828 25.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP1 clock is much faster than the system clock. In Slave mode, when MSSP1 interrupts are enabled, after the master completes sending data, an MSSP1 interrupt will wake the controller from Sleep.
PIC16(L)F1824/1828 25.3 I2C Mode Overview FIGURE 25-11: The Inter-Integrated Circuit Bus (I²C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 25-2 and Figure 25-3 shows the block diagram of the MSSP1 module when operating in I2C Mode.
PIC16(L)F1824/1828 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration.
PIC16(L)F1824/1828 25.4.4 SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSP1CON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. TABLE 25-2: TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus.
PIC16(L)F1824/1828 25.4.5 START CONDITION has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. 2 The I C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state.
PIC16(L)F1824/1828 25.4.9 ACKNOWLEDGE SEQUENCE 25.5 The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
PIC16(L)F1824/1828 25.5.2 SLAVE RECEPTION 25.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSP1STAT register is cleared. The received address is loaded into the SSP1BUF register and acknowledged. Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCL.
2010-2012 Microchip Technology Inc. SSPOV BF SSP1IF S 1 A7 2 A6 3 A5 4 A4 5 A3 Receiving Address 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 5 D3 6 D2 7 D1 SSP1BUF is read Cleared by software 3 D4 Receiving Data D5 8 9 2 D6 First byte of data is available in SSP1BUF 1 D0 ACK D7 4 5 D3 6 D2 7 D1 SSPOV set because SSP1BUF is still full. ACK is not sent.
DS41419D-page 262 CKP SSPOV BF SSP1IF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSP1BUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSP1BUF 6 D2 7 D1 SSPOV set because SSP1BUF is still full. ACK is not sent.
2010-2012 Microchip Technology Inc.
DS41419D-page 264 P S ACKTIM CKP ACKDT BF SSP1IF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSP1BUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received d
PIC16(L)F1824/1828 25.5.3 SLAVE TRANSMISSION 25.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSP1STAT register is set. The received address is loaded into the SSP1BUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave.
DS41419D-page 266 P S D/A R/W ACKSTAT CKP BF SSP1IF S 1 2 5 6 7 8 Received address is read from SSP1BUF 4 Indicates an address has been received R/W is copied from the matching address byte When R/W is set SCL is always held low after 9th SCL falling edge 3 9 Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSP1BUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not AC
PIC16(L)F1824/1828 25.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSP1CON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSP1IF interrupt is set. Figure 25-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
DS41419D-page 268 D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSP1IF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSP1BUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC16(L)F1824/1828 25.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 25.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD This section describes a standard sequence of events for the MSSP1 module configured as an I2C Slave in 10-bit Addressing mode. Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSP1ADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same.
DS41419D-page 270 CKP UA BF SSP1IF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low 9 ACK If address matches SSP1ADD it is loaded into SSP1BUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSP1ADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSP1BUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Re
2010-2012 Microchip Technology Inc.
DS41419D-page 272 D/A R/W ACKSTAT CKP UA BF SSP1IF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSP1ADD must be updated SSP1BUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSP1ADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching a
PIC16(L)F1824/1828 25.5.6 CLOCK STRETCHING 25.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching.
PIC16(L)F1824/1828 25.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC16(L)F1824/1828 25.6 I2C Master Mode Master mode is enabled by setting and clearing the appropriate SSP1M bits in the SSP1CON1 register and by setting the SSP1EN bit. In Master mode, the SCL and SDA lines are set as inputs and are manipulated by the MSSP1 hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP1 module is disabled.
PIC16(L)F1824/1828 25.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD<7:0> and begins counting.
PIC16(L)F1824/1828 25.6.4 I2C MASTER MODE START CONDITION TIMING register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSP1CON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD<7:0> and starts its count.
PIC16(L)F1824/1828 25.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING SSP1CON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSP1STAT register will be set. The SSP1IF bit will not be set until the Baud Rate Generator has timed out.
PIC16(L)F1824/1828 25.6.6 I2C MASTER MODE TRANSMISSION 25.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSP1BUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted.
DS41419D-page 280 S R/W PEN SEN BF (SSP1STAT<0>) SSP1IF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSP1BUF written 1 D7 1 SCL held low while CPU responds to SSP1IF ACK = 0 R/W = 0 SSP1BUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSP1BUF is written by software Cleared by software service routine from SSP1 interrupt 2 D6 Transmitt
PIC16(L)F1824/1828 25.6.7 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSP1CON2 register. Note: The MSSP1 module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSP1SR.
DS41419D-page 282 RCEN ACKEN SSPOV BF (SSP1STAT<0>) SDA = 0, SCL = 1 while CPU responds to SSP1IF SSP1IF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 A1 8 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSP1IF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA\ = ACKDT = 0 Cleared in softwa
PIC16(L)F1824/1828 25.6.8 ACKNOWLEDGE SEQUENCE TIMING 25.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSP1CON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16(L)F1824/1828 FIGURE 25-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSP1STAT<4>) is set. Write to SSP1CON2, set PEN PEN bit (SSP1CON2<2>) is cleared by hardware and the SSP1IF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. 25.6.
PIC16(L)F1824/1828 FIGURE 25-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn’t match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 25.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 25-33). SCL is sampled low before SDA is asserted low (Figure 25-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 25-35).
PIC16(L)F1824/1828 FIGURE 25-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF.
PIC16(L)F1824/1828 25.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 25-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC16(L)F1824/1828 25.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSP1ADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 25-38).
PIC16(L)F1824/1828 TABLE 25-3: Name INLVLB(1) SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 INLVLB7 (1) INLVLC7 INLVLC Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INLVLB6 INLVLB5 INLVLB4 — — — — 133 INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 139 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 95 PIR1
PIC16(L)F1824/1828 25.7 Baud Rate Generator The MSSP1 module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSP1ADD register (Register 25-6). When a write occurs to SSP1BUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line.
PIC16(L)F1824/1828 REGISTER 25-1: SSP1STAT: SSP1 STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data
PIC16(L)F1824/1828 REGISTER 25-2: SSP1CON1: SSP1 CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mod
PIC16(L)F1824/1828 REGISTER 25-3: SSP1CON2: SSP1 CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bi
PIC16(L)F1824/1828 REGISTER 25-4: SSP1CON3: SSP1 CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus i
PIC16(L)F1824/1828 REGISTER 25-5: R/W-1/1 SSP1MSK: SSP1 MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSP1ADD to detect I2C address match 0 = The received addres
PIC16(L)F1824/1828 26.
PIC16(L)F1824/1828 FIGURE 26-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGH SPBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA
PIC16(L)F1824/1828 26.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F1824/1828 26.1.1.4 TSR Status 26.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 26.1.1.5 1. 2. 3.
PIC16(L)F1824/1828 FIGURE 26-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG TX/CK pin Start bit Stop bit Start bit bit 0 Word 2 Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 APFCON0 RXDTSEL SDOSEL(2) BAUDCON ABDOVF INLVLA bit 7/8 This timing diagram shows two consecutive transmissions. TABLE 26-1: (3) bit 1 Word 1 1 TCY TRMT bit (Transmit Shift Reg.
PIC16(L)F1824/1828 26.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 26-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16(L)F1824/1828 26.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16(L)F1824/1828 26.1.2.8 Asynchronous Reception Setup: 26.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 26.3 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register.
PIC16(L)F1824/1828 TABLE 26-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 APFCON0 RXDTSEL SDOSEL(2) BAUDCON ABDOVF Bit 1 Bit 0 Register on Page Bit 4 Bit 3 Bit 2 SSSEL(2) — T1GSEL TXCKSEL — — 122 RCIDL — SCKP BRG16 — WUE ABDEN 310 INLVLA(3) — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 128 INLVLB(1) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 133 INLVLC INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INL
PIC16(L)F1824/1828 26.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 26-1: The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output.
PIC16(L)F1824/1828 RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) REGISTER 26-2: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/C
PIC16(L)F1824/1828 REGISTER 26-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto
PIC16(L)F1824/1828 26.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer.
PIC16(L)F1824/1828 TABLE 26-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 FOSC/[16 (n+1)] FOSC/[4 (n+1)] Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair TABLE 26-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5
PIC16(L)F1824/1828 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.
PIC16(L)F1824/1828 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC16(L)F1824/1828 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.
PIC16(L)F1824/1828 26.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 26.3.3 “Auto-Wake-up on Break”).
PIC16(L)F1824/1828 26.3.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC16(L)F1824/1828 FIGURE 26-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC16(L)F1824/1828 26.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC16(L)F1824/1828 26.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F1824/1828 FIGURE 26-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
PIC16(L)F1824/1828 26.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16(L)F1824/1828 FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F1824/1828 26.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16(L)F1824/1828 26.4.2.3 EUSART Synchronous Slave Reception 26.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 26.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F1824/1828 26.5 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 26.5.
PIC16(L)F1824/1828 27.0 CAPACITIVE SENSING (CPS) MODULE The Capacitive Sensing (CPS) module allows for an interaction with an end user without a mechanical interface. In a typical application, the CPS module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the capacitive sensing module.
PIC16(L)F1824/1828 FIGURE 27-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM Oscillator Module VDD (1) + (2) - S CPSx (1) Analog Pin - Q CPSCLK R (2) + Internal References Ref- 0 0 Ref+ 1 DAC 1 FVR CPSRM Note 1: 2: Module Enable and Power mode selections are not shown. Comparators remain active in Noise Detection mode. DS41419D-page 328 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 27.1 Analog MUX The capacitive sensing module can monitor up to four inputs for the PIC16(L)F1824 (CPSCH<7:0>) and up to eight inputs for the PIC16(L)F1828 (CPSCH<11:0>). See Register 27-2 for details. The capacitive sensing inputs are defined as CPS<11:0>, as applicable to device.
PIC16(L)F1824/1828 27.4 The Noise Detection mode is unique in that it disables the constant current source associated with the selected input pin, but leaves the rest of the oscillator circuitry and pin structure active. This eliminates the oscillation frequency on the analog pin and greatly reduces the current consumed by the Oscillator module. When noise is introduced onto the pin, the oscillator is driven at the frequency determined by the noise.
PIC16(L)F1824/1828 27.5 Timer Resources 27.7 To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base. 27.
PIC16(L)F1824/1828 27.7.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed information on the software required for capacitive sensing module. Note: For more information on general capacitive sensing refer to Application Notes: 27.
PIC16(L)F1824/1828 REGISTER 27-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 U-0 CPSON CPSRM — — R/W-0/0 R/W-0/0 CPSRNG<1:0> R-0/0 R/W-0/0 CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSON: Capacitive Sensing Module Enable bit 1 = CPS module is enabled 0 = CPS mod
PIC16(L)F1824/1828 REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 — — — — R/W-0/0(1) R/W-0/0 R/W-0/0 R/W-0/0 CPSCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: Thes
PIC16(L)F1824/1828 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications.
PIC16(L)F1824/1828 28.2 FIGURE 28-2: Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC16F/LF1824/1828 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. VDD Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2.
PIC16(L)F1824/1828 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 28-4 for more information.
PIC16(L)F1824/1828 NOTES: DS41419D-page 338 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16(L)F1824/1828 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (litera
PIC16(L)F1824/1828 TABLE 29-3: PIC16F/LF1824/1828 ENHANCED INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Sh
PIC16(L)F1824/1828 TABLE 29-3: PIC16F/LF1824/1828 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPT
PIC16(L)F1824/1828 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: (W) .AND. (k) (W) Operation: FSR(n) + k FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.
PIC16(L)F1824/1828 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16(L)F1824/1828 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>.
PIC16(L)F1824/1828 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1824/1828 LSLF Logical Left Shift MOVF Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F1824/1828 MOVIW Move INDFn to W MOVLP Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Syntax: [ label ] MOVLP k Operands: 0 k 127 Operands: n [0,1] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Sta
PIC16(L)F1824/1828 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] MOVWI ++INDFn [ label ] MOVWI --INDFn [ label ] MOVWI INDFn++ [ label ] MOVWI INDFn-[ label ] MOVWI k[FSRn] Syntax: [ label ] Operands: None n [0,1] -32 k 31 Description: No operation.
PIC16(L)F1824/1828 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] None RETFIE RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16(L)F1824/1828 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC16(L)F1824/1828 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F1824/1828 30.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F1824/1828 .................................................................... -0.
PIC16(L)F1824/1828 PIC16F1824/1828 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 30-1: VDD (V) 5.5 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies. PIC16LF1824/1828 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 30-2: 3.6 2.5 1.
PIC16(L)F1824/1828 FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 25 ± 2% 0 -20 -40 1.8 ± 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 30.1 DC Characteristics: PIC16(L)F1824/1828-I/E (Industrial, Extended) PIC16LF1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD D001 D002* VDR D002* Characteristic Min. Typ† Max.
PIC16(L)F1824/1828 FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 30.2 DC Characteristics: PIC16(L)F1824/1828-I/E (Industrial, Extended) PIC16LF1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC16(L)F1824/1828 30.2 DC Characteristics: PIC16(L)F1824/1828-I/E (Industrial, Extended) (Continued) PIC16LF1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC16(L)F1824/1828 30.2 DC Characteristics: PIC16(L)F1824/1828-I/E (Industrial, Extended) (Continued) PIC16LF1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics D019 Conditions Min. Typ† Max.
PIC16(L)F1824/1828 30.3 DC Characteristics: PIC16(L)F1824/1828-I/E (Power-Down) PIC16LF1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Conditions Max. +85°C Max.
PIC16(L)F1824/1828 30.3 DC Characteristics: PIC16(L)F1824/1828-I/E (Power-Down) (Continued) PIC16LF1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1824/1828 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Conditions Max. +85°C Max.
PIC16(L)F1824/1828 30.4 DC Characteristics: PIC16(L)F1824/1828-I/E DC CHARACTERISTICS Param No. Sym. VIL Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Characteristic Min. Typ† Max. Units — — with Schmitt Trigger buffer Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.0V VDD 5.5V with I2C™ levels — — 0.
PIC16(L)F1824/1828 30.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RA5 pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.
PIC16(L)F1824/1828 30.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic Typ. Units JA Thermal Resistance Junction to Ambient 70.0 C/W 14-pin PDIP package 95.3 C/W 14-pin SOIC package 100.0 C/W 14-pin TSSOP package 45.7 C/W 16-pin QFN (4x4mm) package 62.2 C/W 20-pin PDIP package 77.7 C/W 20-pin SOIC package 87.3 C/W 20-pin SSOP package 43.
PIC16(L)F1824/1828 30.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F1824/1828 30.8 AC Characteristics: PIC16(L)F1824/1828-I/E FIGURE 30-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym.
PIC16(L)F1824/1828 TABLE 30-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS08 Freq. Tolerance Min. Typ† Max. Units Internal Calibrated HFINTOSC Frequency (NOTE 1) 2% — 16.0 — MHz 0°C TA +60°C, VDD 2.5V 3% — 16.0 — MHz 60°C TA +85°C, VDD 2.5V 5% — 16.0 — MHz -40°C TA +125°C Internal Calibrated MFINTOSC Frequency (NOTE 1) 2% — 500 — kHz 0°C TA +60°C, VDD 2.5V Sym.
PIC16(L)F1824/1828 FIGURE 30-7: Cycle CLKOUT AND I/O TIMING Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS16 OS13 OS18 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions OS11 TosH2ckL FOSC to CLKOUT (NOTE 1) — — 70 ns VDD = 3.0-5.0V OS12 TosH2ckH FOSC to CLKOUT (NOTE 1) — — 72 ns VDD = 3.0-5.
PIC16(L)F1824/1828 FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 33(1) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’. 2 ms delay if PWRTE = 0 and VREGEN = 1. 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max.
PIC16(L)F1824/1828 TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler — — ns — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.
PIC16(L)F1824/1828 TABLE 30-8: PIC16(L)F1824/1828 A/D CONVERTER (ADC) CHARACTERISTICS (NOTE 1, 2, 3) Standard Operating Conditions (unless otherwise stated) Operating temperature TA 25°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — — ±1.7 AD03 EDL Differential Error — — ±1 AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V AD05 EGN LSb VREF = 3.
PIC16(L)F1824/1828 FIGURE 30-12: PIC16(L)F1824/1828 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16(L)F1824/1828 TABLE 30-10: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym. Characteristics Min. Typ. Max. Units — ±7.
PIC16(L)F1824/1828 TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. Max. Units — 80 ns US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time (Master mode) 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.
PIC16(L)F1824/1828 FIGURE 30-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDOx LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions.
PIC16(L)F1824/1828 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE = 0) SSx SP70 SCKx (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 MSb SDOx LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions.
PIC16(L)F1824/1828 TABLE 30-14: SPI MODE REQUIREMENTS Param No. Symbol Characteristic Min. Typ† Max.
PIC16(L)F1824/1828 FIGURE 30-20: I2C™ BUS START/STOP BITS TIMING SCLx SP93 SP91 SP90 SP92 SDAx Stop Condition Start Condition Note: Refer to Figure 30-5 for load conditions. TABLE 30-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 THD:STO * Characteristic Min. Typ Max.
PIC16(L)F1824/1828 TABLE 30-16: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH SP101* TLOW SP102* TR SP103* TF SP106* THD:DAT SP107* TSU:DAT SP109* TAA SP110* SP111 * Note 1: 2: TBUF CB Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSPx module 1.5TCY — — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.
PIC16(L)F1824/1828 TABLE 30-17: CAP SENSE OSCILLATOR SPECIFICATIONS Param. No. Symbol CS01* ISRC CS02* ISNK Characteristic Current Source Current Sink Min. Typ† Max. Units High — -8 — A Medium — -1.5 — A Low — -0.3 — A High — 7.5 — A Medium — 1.5 — A — 0.25 — A — 0.8 — V Low CS03* VCTH Cap Threshold CS04* VCTL Cap Threshold CS05* VCHYST Cap Hysteresis (VCTH - VCTL) — 0.
PIC16(L)F1824/1828 NOTES: DS41419D-page 384 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16(L)F1824/1828 FIGURE 31-1: IDD, LP OSCILLATOR MODE (FOSC = 32 kHz), PIC16LF1824/1828 ONLY 12 Max: 85°C + 3 Typical: 25°C 10 Max. IDD (μA) 8 Typical 6 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD, LP OSCILLATOR MODE (FOSC = 32 kHz), PIC16F1824/1828 ONLY FIGURE 31-2: 45 Max: 85°C + 3 Typical: 25°C 40 Max. 35 IDD (μA) 30 Typical 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41419D-page 386 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1824/1828 ONLY 400 4 MHz XT Typical: 25°C 350 4 MHz EXTRC 300 IDD (μA) 250 200 1 MHz XT 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1824/1828 ONLY 450 Max: 85°C + 3 400 4 MHz XT 350 4 MHz EXTRC IDD (μA) 300 250 200 1 MHz XT 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1824/1828 FIGURE 31-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1824/1828 ONLY 500 4 MHz EXTRC Typical: 25°C 450 4 MHz XT 400 350 IDD (μA) 300 250 200 150 1 MHz XT 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1824/1828 ONLY 600 Max: 85°C + 3 4 MHz EXTRC 500 4 MHz XT IDD (μA) 400 300 200 1 MHz XT 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1824/1828 FIGURE 31-7: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1824/1828 ONLY 350 4 MHz Typical: 25°C 300 IDD (μA) 250 200 150 1 MHz 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.4 3.6 3.8 VDD (V) FIGURE 31-8: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1824/1828 ONLY 400 Max: 85°C + 3 350 4 MHz 300 IDD (μA) 250 200 150 1 MHz 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-9: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1824/1828 ONLY 450 4 MHz 400 Typical: 25°C 350 IDD (μA) 300 250 200 1 MHz 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.0 VDD (V) FIGURE 31-10: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1824/1828 ONLY 500 4 MHz Max: 85°C + 3 450 400 IDD (μA) 350 300 250 200 1 MHz 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
PIC16(L)F1824/1828 FIGURE 31-11: IDD, LFINTOSC MODE (FOSC = 31 kHz), PIC16LF1824/1828 ONLY 12 Max. 10 Typical IDD (μA) 8 6 4 Max: 85°C + 3 Typical: 25°C 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-12: IDD, LFINTOSC MODE (FOSC = 31 kHz), PIC16F1824/1828 ONLY 40 Max. 35 IDD (μA) 30 Typical 25 20 15 10 Max: 85°C + 3 Typical: 25°C 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-13: IDD, MFINTOSC MODE (FOSC = 500 kHz), PIC16LF1824/1828 ONLY 160 Max. Max: 85°C + 3 Typical: 25°C 150 Typical IDD (μA) 140 130 120 110 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-14: IDD, MFINTOSC MODE (FOSC = 500 kHz), PIC16F1824/1828 ONLY 240 Max. Max: 85°C + 3 Typical: 25°C 220 Typical IDD (μA) 200 180 160 140 120 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1824/1828 FIGURE 31-15: IDD TYPICAL, HFINTOSC MODE, PIC16LF1824/1828 ONLY 3.5 32 MHz (PLL) Typical: 25°C 3.0 IDD (mA) 2.5 2.0 16 MHz 1.5 8 MHz 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.6 3.8 VDD (V) FIGURE 31-16: IDD MAXIMUM, HFINTOSC MODE, PIC16LF1824/1828 ONLY 3.5 32 MHz (PLL) Max: 85°C + 3 3.0 IDD (mA) 2.5 2.0 16 MHz 1.5 8 MHz 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-17: IDD TYPICAL, HFINTOSC MODE, PIC16F1824/1828 ONLY 3.0 32 MHz (PLL) Typical: 25°C 2.5 IDD (mA) 2.0 16 MHz 1.5 8 MHz 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.0 VDD (V) FIGURE 31-18: IDD MAXIMUM, HFINTOSC MODE, PIC16F1824/1828 ONLY 3.0 32 MHz (PLL) Max: 85°C + 3 2.5 2.0 IDD (mA) 16 MHz 1.5 8 MHz 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) DS41419D-page 394 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-19: IDD, HS OSCILLATOR, 32 MHz (8 MHz + 4xPLL), PIC16LF1824/1828 ONLY 3.5 Max 3.0 Typical: 25°C Typical IDD (mA) 2.5 2.0 1.5 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-20: IDD, HS OSCILLATOR, 32 MHz (8 MHz + 4xPLL), PIC16F1824/1828 ONLY 3.5 Max 3.0 Typical: 25°C 2.5 Typical IDD (mA) 2.0 1.5 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-21: IPD BASE, LOW-POWER SLEEP MODE, PIC16LF1824/1828 ONLY 0.40 0.35 Max. IPD (μA) 0.30 Max: 85°C + 3 Typical: 25°C 0.25 0.20 0.15 0.10 Typical 0.05 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 VDD (V) FIGURE 31-22: IPD BASE, LOW-POWER SLEEP MODE, PIC16F1824/1828 ONLY 50 Max: 85°C + 3 M 3 Typical: 25°C 45 40 IPD (μA) 35 Max. 30 25 20 Typical 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1824/1828 FIGURE 31-23: IPD, WATCHDOG TIMER (WDT), PIC16LF1824/1828 ONLY 0.9 Max. Max: 85°C + 3 Typical: 25°C 0.8 0.7 IPD (μA) 0.6 0.5 0.4 Typical 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-24: IPD, WATCHDOG TIMER (WDT), PIC16F1824/1828 ONLY 35 Max. Max: 85°C + 3 M 3 Typical: 25°C 30 IPD (μA A) 25 20 Typical yp 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-25: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1824/1828 ONLY 18 16 Max. 14 12 IPD (μA A) Typical 10 8 6 4 Max: 85°C + 3 yp Typical: 25°C 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-26: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1824/1828 ONLY 90 Max Max. 80 Max: 85°C + 3 Typical: 25°C 70 IPD (μA) 60 Typical 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1824/1828 FIGURE 31-27: IPD, BROWN-OUT RESET (BOR), PIC16LF1824/1828 ONLY 11 Max. Max: 85°C + 3 Typical: 25°C 10 9 IPD (μA) 8 7 Typical 6 5 4 1 8 1.8 2 0 2.0 2 2 2.2 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 VDD (V) FIGURE 31-28: IPD, BROWN-OUT RESET (BOR), PIC16F1824/1828 ONLY 40 Max. Max: 85°C + 3 Typical: 25°C 35 30 25 IPD (μA) Typical 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-29: IPD, TIMER1 OSCILLATOR (FOSC = 32 kHz), PIC16LF1824/1828 ONLY 6.0 Max: 85°C + 3 Typical: 25°C 5.0 Max. IPD (μA A) 4.0 3.0 Typical 2.0 1.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IPD, TIMER1 OSCILLATOR (FOSC = 32 kHz), PIC16F1824/1828 ONLY FIGURE 31-30: 35 30 Max. IPD (μA) 25 Typical 20 15 10 Max: 85°C + 3 Typical: 25°C 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1824/1828 FIGURE 31-31: IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE, CPSRM = 0, PIC16LF1824/1828 ONLY 6 Max: 85°C + 3 M 3 Typical: 25°C 5 Max. IPD (μA A) 4 Typical yp 3 2 1 0 1 6 1.6 1 8 1.8 2 0 2.0 2 2 2.2 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 VDD (V) FIGURE 31-32: IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE, CPSRM = 0, PIC16F1824/1828 ONLY 40 Max.
PIC16(L)F1824/1828 FIGURE 31-33: IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE, CPSRM = 0, PIC16LF1824/1828 ONLY 10 Max Max. Max: 85°C + 3 Typical: 25°C 9 8 7 Typical IPD D (μA) 6 5 4 3 2 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE, CPSRM = 0, PIC16F1824/1828 ONLY FIGURE 31-34: 40 Max. 35 30 Typical IPD (μA A) 25 20 15 10 Max: 85°C + 3 yp Typical: 25°C 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.
PIC16(L)F1824/1828 FIGURE 31-35: IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE, CPSRM = 0, PIC16LF1824/1828 ONLY 40 Max. Max: 85°C + 3 M 3 Typical: 25°C 35 30 Typical IPD (μA A) 25 20 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-36: IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE, CPSRM = 0, PIC16F1824/1828 ONLY 80 Max: 85°C + 3 Typical: 25°C 70 Max. 60 Typical IPD (μA A) 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
PIC16(L)F1824/1828 FIGURE 31-37: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16LF1824/1828 ONLY 10 9 Max. 8 7 IPD (μA) Typical 6 5 4 3 2 Max: 85°C + 3 Typical: 25°C 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-38: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16F1824/1828 ONLY 45 Max Max. 40 35 IPD (μA) 30 Typical yp 25 20 15 10 Max: 85°C + 3 yp Typical: 25°C 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1824/1828 FIGURE 31-39: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC16LF1824/1828 ONLY 30 Max. 25 IPD (μA A) 20 Typical 15 10 Max: 85°C + 3 Typical: 25°C 5 0 16 1.6 1 8 1.8 2 0 2.0 2 2 2.2 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 VDD (V) FIGURE 31-40: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC16F1824/1828 ONLY 60 Max. 50 40 IPD (μA A) Typical 30 20 Max: 85°C + 3 Typical: 25°C 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1824/1828 FIGURE 31-41: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V), PIC16F1824/1828 ONLY 6 Graph represents 3 Limits 5 VOH (V) 4 -40°C 3 125°C 2 Typical 1 0 -30 -25 -20 -15 -10 -5 0 IOH (mA) FIGURE 31-42: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V), PIC16F1824/1828 ONLY 5 Graph represents 3 Limits VOL (V) 4 3 -40°C 2 Typical 125°C 1 0 0 DS41419D-page 406 10 20 30 40 IOL (mA) 50 60 70 80 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-43: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 Graph represents 3 Limits 3.0 VOH (V) 2.5 2.0 1.5 125°C Typical 1.0 -40°C 0.5 0.0 -14 -12 -10 -8 -6 -4 -2 0 IOH (mA) FIGURE 31-44: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) 3.0 Graph represents 3 Limits 2.5 VOL (V) 2.0 -40°C Typical 1.5 125°C 1.0 0.5 0.0 0 5 10 15 20 25 30 IOL (mA) 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-45: VOH vs. IOH OVER TEMPERATURE (VDD = 1.8V) 2.0 Graph represents 3 Limits 1.8 1.6 VOH (V) 1.4 1.2 125°C 1.0 0.8 Typical -40°C 0.6 0.4 0.2 0.0 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 IOH (mA) FIGURE 31-46: VOL vs. IOL OVER TEMPERATURE (VDD = 1.8V) 1.8 Graph represents 3 Limits 1.6 1.4 VOL (V) 1.2 1.0 125°C Typical 0.8 -40°C 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) DS41419D-page 408 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 FIGURE 31-47: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 Voltage (V) 1.64 Typical 1.62 Min. 1.60 1.58 1.56 Max: Typical + 3 Typical: 25°C Min: Typical - 3 1.54 1.52 1.50 -40 -20 0 20 40 60 80 100 120 100 120 Temperature (°C) FIGURE 31-48: POR REARM VOLTAGE, PIC16F1824/1828 ONLY 1.54 Max: Typical + 3 Typical: 25°C Min: Typical - 3 1.52 1.50 Max. Voltage (V) 1.48 1.46 1.44 Typical 1.42 1.40 Min. 1.38 1.36 1.
PIC16(L)F1824/1828 FIGURE 31-49: BROWN-OUT RESET VOLTAGE, BORV = 1 2.10 Max: Typical + 3 Min: Typical - 3 2.05 2.00 Voltage (V) Max. 1.95 1.90 Min. 1.85 1.80 1.75 1.70 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-50: BROWN-OUT RESET HYSTERESIS, BORV = 1 70 Max. 60 Voltage (mV) 50 Typical 40 30 Min.
PIC16(L)F1824/1828 FIGURE 31-51: BROWN-OUT RESET VOLTAGE, BORV = 0 2.90 2.85 Max: Typical + 3 Min: Typical - 3 2.80 Max. Voltage (V) 2.75 2.70 2.65 Min. 2.60 2.55 2.50 2.45 2.40 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-52: BROWN-OUT RESET HYSTERESIS, BORV = 0 90 80 Max. 70 Voltage (mV) 60 50 Typical 40 30 20 Max: Typical + 3 Typical: 25°C Min: Typical - 3 Min.
PIC16(L)F1824/1828 FIGURE 31-53: WDT TIME-OUT PERIOD 24 22 Max. Time (mS) 20 18 Typical 16 14 Min. Max: Typical + 3 (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3 (-40°C to +125°C) 12 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Voltage (V) FIGURE 31-54: PWRT PERIOD 110 100 Max. Time (mS) 90 80 Typical 70 Min. 60 Max: Typical + 3 (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3 (-40°C to +125°C) 50 40 1.5 2 2.5 3 3.5 4 4.5 5 5.
PIC16(L)F1824/1828 FIGURE 31-55: COMPARATOR HYSTERESIS, NORMAL-POWER MODE (CxSP = 1, CxHYS = 1) 80 70 Max. Hysteresis (mV) 60 Typical 50 40 Min. 30 20 Max: Typical + 3 Typical: 25°C Min: Typical - 3 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-56: COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1) 16 14 Max. Hysteresis (mV) 12 Typical 10 8 Min. 6 4 Max: Typical + 3 Typical: 25°C Min: Typical - 3 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1824/1828 FIGURE 31-57: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE (CxSP = 1) 350 300 Time (nS) 250 Max. 200 Typical 150 100 Max: Typical + 3 Typical: 25°C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-58: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER MODE (CxSP = 1) 400 Graph represents 3 Limits 350 Time (nS) 300 250 125°C 200 150 Typical 100 -40°C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1824/1828 FIGURE 31-59: COMPARATOR INPUT OFFSET AT 25°C, NORMAL-POWER MODE (CxSP = 1), PIC16F1824/1828 ONLY 50 40 30 Max. Offset Voltage (mV) 20 10 Typical 0 Min. -10 -20 Max: Typical + 3 Typical: 25°C Min: Typical - 3 -30 -40 -50 0.0 1.0 2.0 3.0 4.0 5.0 Common Mode Voltage (V) 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 NOTES: DS41419D-page 416 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 32.
PIC16(L)F1824/1828 32.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 32.
PIC16(L)F1824/1828 32.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F1824/1828 32.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 32.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F1824/1828 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 14-Lead PDIP (300 mil) Example PIC16LF1824 -E/P e3 1220123 14-Lead SOIC (3.90 mm) Example PIC16LF1824 -E/SL e3 1220123 Example 14-Lead TSSOP (4.4 mm) XXXXXXXX YYWW NNN Legend: XX...
PIC16(L)F1824/1828 33.2 Package Marking Information (Continued) 16-Lead QFN (4x4x0.9 mm) PIN 1 Example PIN 1 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SOIC (7.50 mm) EML e3 PIC16 LF1824 220123 Example PIC16LF1828 -E/P e3 1220123 Example PIC16F1828 -E/SO e3 1220123 Legend: XX...
PIC16(L)F1824/1828 33.3 Package Marking Information (Continued) 20-Lead SSOP (5.30 mm) Example PIC16LF1828 -E/SS e3 1220123 20-Lead QFN (4x4x0.9 mm) PIN 1 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: * Example PIC16 LF1828 E/ML e3 220123 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
PIC16(L)F1824/1828 33.4 Package Details The following sections give the technical details of the packages. 4 & ' !& " & 5 # * !( ! ! & && 366*** ' '6 5 5 % & & # & N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 7 &! ' ! : ' &! 8"') % ! 8 & 8,9.
PIC16(L)F1824/1828 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41419D-page 426 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 4 & ' !& " & 5 # * !( ! ! & && 366*** ' '6 5 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41419D-page 428 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41419D-page 430 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 ! " # $ % & ' ( ( )* "# 4 & ' !& " & 5 # * !( ! ! & && 366*** ' '6 5 5 % & & # & D2 D EXPOSED PAD e E2 E 2 2 1 1 b TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 7 &! ' ! : ' &! 8"') % ! :: . . 8 8 8; < @ & ; 9 & ? & # %% 1 , & & 5 !! - ; > #& . .$ .
PIC16(L)F1824/1828 4 & ' !& " & 5 # * !( ! ! & && 366*** ' '6 5 DS41419D-page 432 5 % & & # & 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 + 4 & ' !& " & 5 # * !( ! ! & && 366*** ' '6 5 5 % & & # & N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 eB e b 7 &! ' ! : ' &! 8"') % ! 8 & 8,9. 8 < & & 8; 2 , = = # # 5 5 !! 1 - 1 2 ! & & 1 = = .
PIC16(L)F1824/1828 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41419D-page 434 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41419D-page 436 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 + ,-. % , / ,, 0) ,,/ 4 & ' !& " & 5 # * !( ! ! & && 366*** ' '6 5 5 % & & # & D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 7 &! ' ! : ' &! 8"') % ! L :: . . 8 8 8; < & ; 9 & = = # # 5 5 !! @1 1 ?1 & # %% 1 = = ; > #& . ? ? # # 5 > #& .
PIC16(L)F1824/1828 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41419D-page 438 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 + " # $ % & ' ( ( )* "# 4 & ' !& " & 5 # * !( ! ! & && 366*** ' '6 5 5 % & & # & D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 7 &! ' ! : ' &! 8"') % ! :: . . 8 8 8; < & ; 9 & ? & # %% 1 , & & 5 !! - ; > #& . .$ .
PIC16(L)F1824/1828 4 & ' !& " & 5 # * !( ! ! & && 366*** ' '6 5 DS41419D-page 440 5 % & & # & 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (06/2010) Original release. APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This section provides comparisons when migrating devices to the from other similar PIC® PIC16F/LF1824/1828 family of devices. Revision B (12/2010) Updated the data sheet to new format; Updated the Electrical Specifications section; Revised Sections 24.2 and 24.3.
PIC16(L)F1824/1828 Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.
PIC16(L)F1824/1828 INDEX A A/D Specifications............................................................ 374 Absolute Maximum Ratings .............................................. 353 AC Characteristics Industrial and Extended ............................................ 367 Load Conditions ........................................................ 366 ACKSTAT ......................................................................... 279 ACKSTAT Status Flag ...................................................
PIC16(L)F1824/1828 CCPR1H Register ......................................................... 36, 37 CCPR1L Register.......................................................... 36, 37 CCPTMRS0 Register ........................................................ 239 CCPxAS Register.............................................................. 240 CCPxCON (ECCPx) Register ........................................... 238 CLKRCON Register ............................................................
PIC16(L)F1824/1828 Associated Registers Receive..................................................... 323 Transmit.................................................... 321 Reception.......................................................... 322 Transmission .................................................... 320 Synchronous Slave Mode Associated Registers Receive..................................................... 325 Transmit.................................................... 324 Reception.................
PIC16(L)F1824/1828 M Master Synchronous Serial Port. See MSSPx MCLR .................................................................................. 81 Internal ........................................................................ 81 MDCARH Register ............................................................ 212 MDCARL Register............................................................. 213 MDCON Register .............................................................. 210 MDSRC Register...............
PIC16(L)F1824/1828 APFCON0 (Alternate Pin Function Control 0)........... 122 APFCON1 (Alternate Pin Function Control 1)........... 123 BAUDCON (Baud Rate Control) ............................... 310 BORCON Brown-out Reset Control)........................... 80 CCPTMRS0 (PWM Timer Selection Control) ........... 239 CCPxAS (CCPx Auto-Shutdown Control)................. 240 CCPxCON (ECCPx Control)..................................... 238 CLKRCON (Reference Clock Control)........................
PIC16(L)F1824/1828 SUBWFB........................................................................... 351 T T1CON Register.......................................................... 31, 197 T1GCON Register............................................................. 198 T2CON Register.................................................................. 31 T4CON Register.................................................................. 39 T6CON Register............................................................
PIC16(L)F1824/1828 Requirements, Synchronous Transmission ...... 377 Timing Diagram, Synchronous Receive ........... 377 Timing Diagram, Synchronous Transmission ... 376 V VREF. SEE ADC Reference Voltage W Wake-up on Break ............................................................ 317 Wake-up Using Interrupts ................................................. 101 Watchdog Timer (WDT) ...................................................... 81 Modes ..........................................................
PIC16(L)F1824/1828 NOTES: DS41419D-page 450 2010-2012 Microchip Technology Inc.
PIC16(L)F1824/1828 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC16(L)F1824/1828 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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