Datasheet

 2010-2012 Microchip Technology Inc. DS41413C-page 97
PIC12(L)F1822/PIC16(L)F1823
8.5.5 PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 8-5.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0
OSFIF C2IF
(1)
C1IF EEIF BCLIF — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 OSFIF: Oscillator Fail Interrupt Flag
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 C2IF: Comparator C2 Interrupt Flag
(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 C1IF: Comparator C1 Interrupt Flag
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2-0 Unimplemented: Read as ‘0’
Note 1: PIC16(L)F1823 only.