Datasheet

 2010-2012 Microchip Technology Inc. DS41413C-page 309
PIC12(L)F1822/PIC16(L)F1823
FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
BAUDCON
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 296
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93
PIE1
TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 94
PIR1
TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 96
RCREG EUSART Receive Data Register 290*
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 295
SPBRGL BRG<7:0> 297*
SPBRGH BRG<15:8> 297*
TRISA
— —
TRISA5
(1)
TRISA4
(1)
TRISA3 TRISA2 TRISA1 TRISA0 126
TRISC
(2)
— —
TRISC5 TRISC4
TRISC3 TRISC2 TRISC1 TRISC0 130
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 294
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
* Page provides register information.
Note 1: PIC12(L)F1822 only.
2: PIC16(L)F1823 only.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)