Datasheet

 2010-2012 Microchip Technology Inc. DS41413C-page 277
PIC12(L)F1822/PIC16(L)F1823
TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 94
PIE2
OSFIE C2IE
(1)
C1IE EEIE BCL1IE
—
— — 95
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF
96
PIR2
OSFIF C2IF
(1)
C1IF EEIF BCL1IF — —
— 97
SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 283
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 237*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 280
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 281
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 282
SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 283
SSP1STAT SMP CKE
D/A P S R/W UA BF 279
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 126
TRISC
— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 130
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I
2
C™ mode.
* Page provides register information.
Note 1: PIC16(L)F1823 only.