Datasheet

 2010-2012 Microchip Technology Inc. DS41413C-page 269
PIC12(L)F1822/PIC16(L)F1823
25.6.7 I
2
C MASTER MODE RECEPTION
Master mode reception (Figure 25-29) is enabled by
programming the Receive Enable bit, RCEN bit of the
SSP1CON2 register.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSP1SR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSP1SR are loaded into the SSP1BUF, the
BF flag bit is set, the SSP1IF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP1 is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSP1CON2 register.
25.6.7.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSP1BUF from SSP1SR. It
is cleared when the SSP1BUF register is read.
25.6.7.2 SSP1OV Status Flag
In receive operation, the SSP1OV bit is set when eight
bits are received into the SSP1SR and the BF flag bit is
already set from a previous reception.
25.6.7.3 WCOL Status Flag
If the user writes the SSP1BUF when a receive is
already in progress (i.e., SSP1SR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
25.6.7.4 Typical Receive Sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSP1CON2 register.
2. SSP1IF is set by hardware on completion of the
Start.
3. SSP1IF is cleared by software.
4. User writes SSP1BUF with the slave address to
transmit and the R/W
bit set.
5. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSP1BUF is written to.
6. The MSSP1 module shifts in the ACK
bit from
the slave device and writes its value into the
ACKSTAT bit of the SSP1CON2 register.
7. The MSSP1 module generates an interrupt at
the end of the ninth clock cycle by setting the
SSP1IF bit.
8. User sets the RCEN bit of the SSP1CON2 regis-
ter and the Master clocks in a byte from the slave.
9. After the 8th falling edge of SCL, SSP1IF and
BF are set.
10. Master clears SSP1IF and reads the received
byte from SSP1UF, clears BF.
11. Master sets ACK
value sent to slave in ACKDT
bit of the SSP1CON2 register and initiates the
ACK
by setting the ACKEN bit.
12. Masters ACK
is clocked out to the Slave and
SSP1IF is set.
13. User clears SSP1IF.
14. Steps 8-13 are repeated for each received byte
from the slave.
15. Master sends a not ACK
or Stop to end
communication.
Note: The MSSP1 module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.