Datasheet

 2010-2012 Microchip Technology Inc. DS41413C-page 265
PIC12(L)F1822/PIC16(L)F1823
FIGURE 25-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
25.6.3 WCOL STATUS FLAG
If the user writes the SSP1BUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSP1BUF
was attempted while the module was not Idle.
25.6.4 I
2
C MASTER MODE START
CONDITION TIMING
To initiate a Start condition (Figure 25-26), the user
sets the Start Enable bit, SEN bit of the SSP1CON2
register. If the SDA and SCL pins are sampled high,
the Baud Rate Generator is reloaded with the contents
of SSP1ADD<7:0> and starts its count. If SCL and
SDA are both sampled high when the Baud Rate Gen-
erator times out (T
BRG), the SDA pin is driven low. The
action of the SDA being driven low while SCL is high is
the Start condition and causes the S bit of the
SSP1STAT1 register to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSP1ADD<7:0> and resumes its count. When the
Baud Rate Generator times out (T
BRG), the SEN bit of
the SSP1CON2 register will be automatically cleared
by hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
FIGURE 25-26: FIRST START BIT TIMING
SDA
SCL
SCL deasserted but slave holds
DX ‚ – 1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
Note: Because queueing of events is not
allowed, writing to the lower five bits of
SSP1CON2 is disabled until the Start
condition is complete.
Note 1: If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCL1IF, is set, the Start condition is
aborted and the I
2
C module is reset into
its Idle state.
2: The Philips I
2
C™ Specification states that
a bus collision cannot occur on a Start.
SDA
SCL
S
TBRG
1st bit
2nd bit
TBRG
SDA = 1,
At completion of Start bit,
SCL = 1
Write to SSP1BUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here
Set S bit (SSP1STAT<3>)
and sets SSP1IF bit