Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 14 8-Bit 32 MHz I/O number 12

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 2010-2012 Microchip Technology Inc. DS41413C-page 249

PIC12(L)F1822/PIC16(L)F1823

25.5.2.2 7-bit Reception with AHEN and

DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the 8th fall-

ing edge of SCL. These additional interrupts allow the

slave software to decide whether it wants to ACK

the

receive address or data byte, rather than the hard-

ware. This functionality adds support for PMBus™ that

was not present on previous versions of this module.

This list describes the steps that need to be taken by

slave software to use these options for I

C communi-

cation. Figure 25-16 displays a module using both

address and data holding. Figure 25-17 includes the

operation with the SEN bit of the SSP1CON2 register

set.

1. S bit of SSP1STAT is set; SSP1IF is set if inter-

rupt on Start detect is enabled.

2. Matching address with R/W

bit clear is clocked

in. SSP1IF is set and CKP cleared after the 8th

falling edge of SCL.

3. Slave clears the SSP1IF.

4. Slave can look at the ACKTIM bit of the

SSP1CON3 register to determine if the SSP1IF

was after or before the ACK.

5. Slave reads the address value from SSP1BUF,

clearing the BF flag.

6. Slave sets ACK

value clocked out to the master

by setting ACKDT.

7. Slave releases the clock by setting CKP.

8. SSP1IF is set after an ACK

, not after a NACK.

9. If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSP1IF.

11. SSP1IF set and CKP cleared after 8th falling

edge of SCL for a received data byte.

12. Slave looks at ACKTIM bit of SSP1CON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSP1BUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK

= 1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSTSTAT register.

Note: SSP1IF is still set after the 9th falling edge

of SCL even if there is no clock stretching

and BF has been cleared. Only if NACK is

sent to Master is SSP1IF not set