Datasheet

 2010-2012 Microchip Technology Inc. DS41413C-page 247
PIC12(L)F1822/PIC16(L)F1823
FIGURE 25-12: I
2
C START AND STOP CONDITIONS
FIGURE 25-13: I
2
C RESTART CONDITION
25.4.9 ACKNOWLEDGE SEQUENCE
The 9th SCL pulse for any transferred byte in I
2
C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK
) is an active-low signal, pulling the
SDA line low indicated to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The result of an ACK
is placed in the ACKSTAT bit of
the SSP1CON2 register.
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK
value sent back to
the transmitter. The ACKDT bit of the SSP1CON2 reg-
ister is set/cleared to determine the response.
Slave hardware will generate an ACK
response if the
AHEN and DHEN bits of the SSP1CON3 register are
clear.
There are certain conditions where an ACK
will not be
sent by the slave. If the BF bit of the SSP1STAT regis-
ter or the SSP1OV bit of the SSP1CON1 register are
set when a byte is received.
When the module is addressed, after the 8th falling
edge of SCL on the bus, the ACKTIM bit of the
SSP1CON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
SDA
SCL
P
Stop
Condition
S
Start
Condition
Change of
Data Allowed
Change of
Data Allowed
Restart
Condition
Sr
Change of
Data Allowed
Change of
Data Allowed