Datasheet

 2010-2012 Microchip Technology Inc. DS41413C-page 237
PIC12(L)F1822/PIC16(L)F1823
FIGURE 25-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION
25.2.1 SPI MODE REGISTERS
The MSSP1 module has five registers for SPI mode
operation. These are:
• MSSP1 STATUS register (SSP1STAT)
• MSSP1 Control Register 1 (SSP1CON1)
• MSSP1 Control Register 3 (SSP1CON3)
• MSSP1 Data Buffer register (SSP1BUF)
• MSSP1 Address register (SSP1ADD)
• MSSP1 Shift register (SSP1SR)
(Not directly accessible)
SSP1CON1 and SSP1STAT are the control and
STATUS registers in SPI mode operation. The
SSP1CON1 register is readable and writable. The
lower 6 bits of the SSP1STAT are read-only. The upper
two bits of the SSP1STAT are read/write.
In one SPI master mode, SSP1ADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 25.7 “Baud Rate Generator”.
SSP1SR is the shift register used for shifting data in
and out. SSP1BUF provides indirect access to the
SSP1SR register. SSP1BUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSP1SR and SSP1BUF
together create a buffered receiver. When SSP1SR
receives a complete byte, it is transferred to SSP1BUF
and the SSP1IF interrupt is set.
During transmission, the SSP1BUF is not buffered. A
write to SSP1BUF will write to both SSP1BUF and
SSP1SR.
25.2.2 SPI MODE OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSP1CON1<5:0> and SSP1STAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK1 is the clock output)
• Slave mode (SCK1 is the clock input)
• Clock Polarity (Idle state of SCK1)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK1)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSP1 Enable bit, SSP1EN of
the SSP1CON1 register must be set. To reset or recon-
figure SPI mode, clear the SSP1EN bit, re-initialize the
SSP1CONx registers and then set the SSP1EN bit.
This configures the SDI, SDO, SCK and SS
pins as
serial port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
•SS
must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
SPI Master
SCK
SDO
SDI
General I/O
General I/O
General I/O
SCK
SDI
SDO
SS
SPI Slave
#1
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3