Datasheet

 2010-2012 Microchip Technology Inc. DS41413C-page 209
PIC12(L)F1822/PIC16(L)F1823
24.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (F
OSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
24.2.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see
Section 12.1 “Alternate Pin Function” for
more information.
TABLE 24-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON
RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL 123
CCP1CON
P1M<1:0> DC1B<1:0> CCP1M<3:0>
228
CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB)
206
CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB)
206
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
93
PIE1 TMR1GIE
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
94
PIE2
OSFIE
C2IE
(1)
C1IE EEIE BCL1IE — — —
95
PIR1 TMR1GIF
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
96
PIR2
OSFIF
C2IF
(1)
C1IF EEIF BCL1IF — — —
97
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
—TMR1ON
187
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0>
188
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
183
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
183
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
126
TRISC
(1)
— —TRISC5TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
130
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
Note 1: PIC16(L)F1823 only.