Datasheet

 2012 Microchip Technology Inc. Preliminary DS41637B-page 201
PIC16(L)F1784/6/7
TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
REGISTER 20-3: CMOUT: COMPARATOR OUTPUT REGISTER
U-0 U-0 U-0 U-0 R-0/0 R-0/0 R-0/0 R-0/0
— — — —MC4OUT
MC3OUT MC2OUT MC1OUT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3
MC4OUT: Mirror Copy of C4OUT bit
bit 2
MC3OUT: Mirror Copy of C3OUT bit
bit 1
MC2OUT: Mirror Copy of C2OUT bit
bit 0
MC1OUT: Mirror Copy of C1OUT bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 135
ANSELB
— ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 141
CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 199
CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 199
CM1CON1 C1NTP C1INTN C1PCH<2:0> C1NCH<2:0> 200
CM2CON1 C2NTP C2INTN C2PCH<2:0> C2NCH<2:0> 200
CM3CON0 C3ON C3OUT C3OE C3POL C3ZLF C3SP C3HYS C3SYNC 199
CM3CON1 C3INTP C3INTN C3PCH<2:0> C3NCH<2:0> 200
CMOUT
— — — — MC4OUT MC3OUT MC2OUT MC1OUT 201
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 163
DACCON0 DACEN
— DACOE1 DACOE2 DACPSS<1:0> — DACNSS 192
DACCON1 DACR<7:0> 192
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 94
PIE2
OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE 96
PIR2
OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF 99
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 135
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 141
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 145
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.