Datasheet

 2012 Microchip Technology Inc. Preliminary DS41637B-page 155
PIC16(L)F1784/6/7
TABLE 13-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
REGISTER 13-36: WPUE: WEAK PULL-UP PORTE REGISTER
U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — — —
WPUE3 WPUE2
(3)
WPUE1
(3)
WPUE0
(3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 WPUE<3:0>: Weak Pull-up Register bit
(3)
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN
bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
3: WPUSE<2:0> are available on PIC16(L)F1784/7 only.
REGISTER 13-37: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — — —
INLVLE3 INLVLE2
(1)
INLVLE1
(1)
INLVLE0
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 INLVLE<3:0>: PORTE Input Level Select bit
(1)
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change
Note 1: INLVLE<2:0> are available on PIC16(L)F1784/7 only.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ADCON0 ADRMD CHS<4:0> GO/DONE
ADON 174
INLVLE
— — — —INLVLE3INLVLE2
(2)
INLVLE1
(2)
INLVLE0
(2)
155
PORTE
— — — —RE3RE2
(2)
RE1
(2)
RE0
(2)
154
TRISE
— — — — —
(1)
TRISE2
(2)
TRISE1
(2)
TRISE0
(2)
154
WPUE
— — — —WPUE3WPUE2
(2)
WPUE1
(2)
WPUE0
(2)
155
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1784/7 only.