Datasheet

 2012 Microchip Technology Inc. Preliminary DS41637B-page 97
PIC16(L)F1784/6/7
REGISTER 8-4: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— PSMC3TIE PSMC2TIE PSMC1TIE — PSMC3SIE PSMC2SIE PSMC1SIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 Unimplemented: Read as ‘0’
bit 6 PSMC3TIE: PSMC3 Time Base Interrupt Enable bit
1 = Enables PSMC3 time base generated interrupts
0 = Disables PSMC3 time base generated interrupts
bit 5 PSMC2TIE: PSMC2 Time Base Interrupt Enable bit
1 = Enables PSMC2 time base generated interrupts
0 = Disables PSMC2 time base generated interrupts
bit 4 PSMC1TIE: PSMC1 Time Base Interrupt Enable bit
1 = Enables PSMC1 time base generated interrupts
0 = Disables PSMC1 time base generated interrupts
bit 3 Unimplemented: Read as ‘0’
bit 2 PSMC3SIE: PSMC3 Auto-Shutdown Interrupt Enable bit
1 = Enables PSMC3 auto-shutdown interrupts
0 = Disables PSMC3 auto-shutdown interrupts
bit 1 PSMC2SIE: PSMC2 Auto-Shutdown Interrupt Enable bit
1 = Enables PSMC2 auto-shutdown interrupts
0 = Disables PSMC2 auto-shutdown interrupts
bit 0 PSMC1SIE: PSMC1 Auto-Shutdown Interrupt Enable bit
1 = Enables PSMC1 auto-shutdown interrupts
0 = Disables PSMC1 auto-shutdown interrupts
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.