Datasheet

 2012 Microchip Technology Inc. Preliminary DS41637B-page 473
PIC16(L)F1784/6/7
Bus Collision During a Start Condition (SCL = 0) ..... 334
Bus Collision During a Stop Condition (Case 1) ....... 336
Bus Collision During a Stop Condition (Case 2) ....... 336
Bus Collision During Start Condition (SDA only) ...... 333
Bus Collision for Transmit and Acknowledge............ 332
Capture/Compare/PWM (CCP)................................. 412
CLKOUT and I/O....................................................... 408
Clock Synchronization .............................................. 321
Clock Timing ............................................................. 406
Comparator Output ................................................... 193
Fail-Safe Clock Monitor (FSCM) ................................. 81
First Start Bit Timing ................................................. 325
I
2
C Bus Data............................................................. 421
I
2
C Bus Start/Stop Bits.............................................. 420
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 328
I
2
C Master Mode (7-Bit Reception)........................... 330
I
2
C Stop Condition Receive or Transmit Mode ......... 331
INT Pin Interrupt.......................................................... 92
Internal Oscillator Switch Timing................................. 76
Repeat Start Condition.............................................. 326
Reset Start-up Sequence............................................ 63
Reset, WDT, OST and Power-up Timer ................... 409
Send Break Character Sequence ............................. 366
SPI Master Mode (CKE = 1, SMP = 1) ..................... 418
SPI Mode (Master Mode).......................................... 297
SPI Slave Mode (CKE = 0) ....................................... 419
SPI Slave Mode (CKE = 1) ....................................... 419
Synchronous Reception (Master Mode, SREN) ....... 370
Synchronous Transmission....................................... 368
Synchronous Transmission (Through TXEN) ........... 368
Timer0 and Timer1 External Clock ........................... 411
Timer1 Incrementing Edge........................................ 211
Two Speed Start-up .................................................... 79
USART Synchronous Receive (Master/Slave) ......... 417
USART Synchronous Transmission (Master/Slave) . 417
Wake-up from Interrupt............................................. 104
Timing Diagrams and Specifications
PLL Clock.................................................................. 407
Timing Parameter Symbology........................................... 405
Timing Requirements
I
2
C Bus Data............................................................. 422
I2C Bus Start/Stop Bits ............................................. 421
SPI Mode .................................................................. 420
TMR0 Register.................................................................... 37
TMR1H Register ................................................................. 37
TMR1L Register.................................................................. 37
TRIS.................................................................................. 390
TRISA Register ........................................................... 37, 134
TRISB ............................................................................... 138
TRISB Register ........................................................... 37, 140
TRISC ............................................................................... 144
TRISC Register........................................................... 37, 145
TRISD ............................................................................... 148
TRISD Register........................................................... 37, 149
TRISE ............................................................................... 153
TRISE Register ........................................................... 37, 154
Two-Speed Clock Start-up Mode........................................ 78
TXREG.............................................................................. 347
TXREG Register ................................................................. 38
TXSTA Register .......................................................... 38, 355
BRGH Bit .................................................................. 358
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 417
Requirements, Synchronous Transmission...... 417
Timing Diagram, Synchronous Receive ........... 417
Timing Diagram, Synchronous Transmission... 417
V
VREF. SEE ADC Reference Voltage
VREGCON Register ......................................................... 106
W
Wake-up on Break............................................................ 364
Wake-up Using Interrupts................................................. 104
Watchdog Timer (WDT)...................................................... 62
Associated Registers................................................ 113
Configuration Word w/ Watchdog Timer................... 113
Modes....................................................................... 110
Specifications ........................................................... 411
WCOL....................................................... 324, 327, 329, 331
WCOL Status Flag.................................... 324, 327, 329, 331
WDTCON Register ........................................................... 112
WPUA Register................................................................. 135
WPUB Register................................................................. 141
WPUC Register ................................................................ 146
WPUD Register ................................................................ 150
Write Protection .................................................................. 57
WWW Address ................................................................. 475
WWW, On-Line Support ................................................. 3, 14