Datasheet
2012 Microchip Technology Inc. Preliminary DS41637B-page 37
PIC16(L)F1784/6/7
TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bank 0
00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu
00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
00Fh PORTD
(3)
PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
010h PORTE
— — — —RE3RE2
(3)
RE1
(3)
RE0
(3)
---- xxxx ---- uuuu
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF 0000 0000 0000 0000
13h PIR3 — — — CCP3IF — — — — ---0 ---- 0000 0000
014h PIR4
— PSMC3TIF PSMC2TIF PSMC1TIF — PSMC3SIF PSMC2SIF PSMC1SIF -000 -000 -000 -000
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—TMR1ON0000 00-0 uuuu uu-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
016h TMR2 Holding Register for the Least Significant Byte of the 16-bit TMR2 Register xxxx xxxx uuuu uuuu
017h PR2 Holding Register for the Most Significant Byte of the 16-bit TMR2 Register xxxx xxxx uuuu uuuu
018h T2CON
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
01Dh
to
01Fh
— Unimplemented — —
Bank 1
08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111
08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111
08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111
08Fh TRISD
(3)
PORTD Data Direction Register 1111 1111 1111 1111
090h TRISE
— — — — —
(2)
TRISE2
(3)
TRISE1
(3)
TRISE0
(3)
---- 1111 ---- 1111
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE 0000 0000 0000 0000
093h PIE3
— — — CCP3IE — — — — ---0 ---- ---0 ----
094h PIE4
— PSMC3TIE PSMC2TIE PSMC1TIE — PSMC3SIE PSMC2SIE PSMC2SIE -000 -000 -000 -000
095h
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
096h PCON STKOVF STKUNF
—RWDTRMCLR RI POR BOR 00-1 11qq qq-q qquu
097h WDTCON
— — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110
098h OSCTUNE
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000
099h OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0
— SCS1 SCS0 0011 1-00 0011 1-00
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR
HFIOFL MFIOFR LFIOFR HFIOFS 00q0 --00 qqqq --0q
09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 ADRMD CHS4 CHS3 CHS2 CHS1 CHS0
GO/DONE
ADON 0000 0000 0000 0000
09Eh ADCON1 ADFM ADCS2 ADCS1 ADCS0
— ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000
09Fh ADCON2 TRIGSEL3 TRIGSEL2 TRIGSEL1 TRIGSEL0 CHSN3 CHSN2 CHSN1 CHSN0 000- -000 000- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: Unimplemented, read as ‘1’.
3: PIC16(L)F1784/6/7 only.