Datasheet

PIC16(L)F1784/6/7
DS41637B-page 262 Preliminary  2012 Microchip Technology Inc.
REGISTER 24-5: PSMC3SYNC: PSMC3 SYNCHRONIZATION CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
P3POFST P3PRPOL P3DCPOL
— — — P3SYNC<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7
P3POFST: PSMC3 Phase Offset Control bit
1 = sync_out source is phase event and latch set source is synchronous period event
0 = sync_out source is period event and latch set source is phase event
bit 6
P3PRPOL: PSMC3 Period Polarity Event Control bit
1 = Selected asynchronous period event inputs are inverted
0 = Selected asynchronous period event inputs are not inverted
bit 5
P3DCPOL: PSMC3 Duty-cycle Event Polarity Control bit
1 = Selected asynchronous duty-cycle event inputs are inverted
0 = Selected asynchronous duty-cycle event inputs are not inverted
bit 4-2
Unimplemented: Read as ‘0’
bit 1-0
P3SYNC<1:0>: PSMC3 Period Synchronization Mode bits
11 = Reserved – Do not use
10 = PSMC3 is synchronized with the PSMC2 module (sync_in comes from PSMC2 sync_out)
01 = PSMC3 is synchronized with the PSMC1 module (sync_in comes from PSMC1 sync_out)
00 = PSMC3 is not synchronized with any other PSMC module