Datasheet

PIC16(L)F1782/3
DS41579D-page 96 Preliminary  2011-2012 Microchip Technology Inc.
9.3 Register Definitions: Voltage Regulator Control
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
REGISTER 9-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER
(1)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — —VREGPMReserved
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Unimplemented: Read as ‘0’
bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep
(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal-Power mode enabled in Sleep
(2)
Draws higher current in Sleep, faster wake-up
bit 0 Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC16F1782/3 only.
2: See Section 30.0 “Electrical Specifications”.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF RAIF 84
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 142
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 141
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 141
PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IFE TMR1IE 85
PIE2 OSFIE C2IE C1IE EEIE BCL1IE
— C3IE CCP2IE 86
PIE4
— — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC2SIE 87
PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88
PIR2 OSFIF C2IF C1IF EEIF BCL1IF
— C3IF CCP2IF 89
PIR4
— — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF 90
STATUS
— — —TOPD ZDCC 23
VREGCON
— — — — — —VREGPMReserved 96
WDTCON
— — WDTPS<4:0> SWDTEN 101
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.