Datasheet

PIC16(L)F1782/3
DS41579D-page 90 Preliminary  2011-2012 Microchip Technology Inc.
REGISTER 8-7: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER42
U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
— — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5 PSMC2TIF: PSMC2 Time Base Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 PSMC1TIF: PSMC1 Time Base Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3-2 Unimplemented: Read as ‘0’
bit 1 PSMC2SIF: PSMC2 Auto-shutdown Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 PSMC1SIF: PSMC1 Auto-shutdown Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.