Datasheet

PIC16(L)F1782/3
DS41579D-page 446 Preliminary  2011-2012 Microchip Technology Inc.
TRISE (Tri-State PORTE)......................................... 137
TXSTA (Transmit Status and Control) ...................... 331
VREGCON (Voltage Regulator Control) ..................... 96
WDTCON (Watchdog Timer Control)........................ 101
WPUA (Weak Pull-up PORTA) ................................. 123
WPUB (Weak Pull-up PORTB) ................................. 129
WPUC (Weak Pull-up PORTC).................................134
RESET ..............................................................................363
Reset Instruction .................................................................52
Resets.................................................................................49
Associated Registers .................................................. 56
Revision History ................................................................ 435
S
SLRCONA Register .......................................................... 124
SLRCONB Register .......................................................... 130
SLRCONC Register .......................................................... 134
Software Simulator (MPLAB SIM)..................................... 421
SPBRG Register .................................................................30
SPBRGH Register.............................................................334
SPBRGL Register ............................................................. 334
Special Function Registers (SFRs) ......................... 29, 34, 35
SPI Mode (MSSP)
Associated Registers ................................................ 277
SPI Clock ..................................................................273
SSPADD Register....................................................... 31, 320
SSPBUF Register ............................................................... 31
SSPCON Register............................................................... 31
SSPCON1 Register........................................................... 317
SSPCON2 Register........................................................... 318
SSPCON3 Register........................................................... 319
SSPMSK Register............................................................. 320
SSPOV.............................................................................. 304
SSPOV Status Flag...........................................................304
SSPSTAT Register ..................................................... 31, 315
R/W
Bit...................................................................... 283
Stack ...................................................................................37
Accessing.................................................................... 37
Reset........................................................................... 39
Stack Overflow/Underflow...................................................52
STATUS Register................................................................23
SUBWFB...........................................................................365
T
T1CON Register.......................................................... 29, 195
T1GCON Register............................................................. 196
T2CON (Timer2) Register .................................................201
Temperature Indicator
Associated Registers ................................................ 148
Temperature Indicator Module .......................................... 147
Thermal Considerations.................................................... 380
Timer0...............................................................................183
Associated Registers ................................................ 185
Operation ..................................................................183
Specifications............................................................ 388
Timer1...............................................................................187
Associated registers..................................................197
Asynchronous Counter Mode ................................... 189
Reading and Writing ......................................... 189
Clock Source Selection.............................................188
Interrupt.....................................................................191
Operation ..................................................................188
Operation During Sleep ............................................191
Oscillator ...................................................................189
Prescaler................................................................... 189
Specifications............................................................ 388
Timer1 Gate
Selecting Source .............................................. 189
TMR1H Register....................................................... 187
TMR1L Register........................................................ 187
Timer2............................................................................... 199
Associated registers ................................................. 202
Timers
Timer1
T1CON ............................................................. 195
T1GCON........................................................... 196
Timer2
T2CON ............................................................. 201
Timing Diagrams
A/D Conversion......................................................... 391
A/D Conversion (Sleep Mode) .................................. 391
Acknowledge Sequence ........................................... 306
Asynchronous Reception.......................................... 328
Asynchronous Transmission..................................... 324
Asynchronous Transmission (Back to Back) ............ 325
Auto Wake-up Bit (WUE) During Normal Operation. 341
Automatic Baud Rate Calibration.............................. 339
Baud Rate Generator with Clock Arbitration............. 299
BRG Reset Due to SDA Arbitration During Start
Condition .......................................................... 310
Brown-out Reset (BOR)............................................ 386
Brown-out Reset Situations ........................................ 51
Bus Collision During a Repeated Start Condition
(Case 1)............................................................ 311
Bus Collision During a Repeated Start Condition
(Case 2)............................................................ 311
Bus Collision During a Start Condition (SCL = 0) ..... 310
Bus Collision During a Stop Condition (Case 1) ....... 312
Bus Collision During a Stop Condition (Case 2) ....... 312
Bus Collision During Start Condition (SDA only) ...... 309
Bus Collision for Transmit and Acknowledge ........... 308
Capture/Compare/PWM (CCP) ................................ 389
CLKOUT and I/O ...................................................... 384
Clock Synchronization .............................................. 296
Clock Timing............................................................. 382
Comparator Output................................................... 173
Fail-Safe Clock Monitor (FSCM)................................. 71
First Start Bit Timing ................................................. 300
I
2
C Bus Data............................................................. 398
I
2
C Bus Start/Stop Bits ............................................. 397
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 303
I
2
C Master Mode (7-Bit Reception)........................... 305
I
2
C Stop Condition Receive or Transmit Mode......... 307
INT Pin Interrupt ......................................................... 82
Internal Oscillator Switch Timing ................................ 66
Repeat Start Condition ............................................. 301
Reset Start-up Sequence ........................................... 53
Reset, WDT, OST and Power-up Timer ................... 385
Send Break Character Sequence ............................. 342
SPI Master Mode (CKE = 1, SMP = 1) ..................... 395
SPI Mode (Master Mode).......................................... 273
SPI Slave Mode (CKE = 0)....................................... 396
SPI Slave Mode (CKE = 1)....................................... 396
Synchronous Reception (Master Mode, SREN) ....... 346
Synchronous Transmission ...................................... 344
Synchronous Transmission (Through TXEN) ........... 344
Timer0 and Timer1 External Clock ........................... 388
Timer1 Incrementing Edge ....................................... 191
Two Speed Start-up.................................................... 69
USART Synchronous Receive (Master/Slave) ......... 393
USART Synchronous Transmission (Master/Slave). 393