Datasheet

PIC16(L)F1782/3
DS41579D-page 346 Preliminary  2011-2012 Microchip Technology Inc.
FIGURE 27-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 27-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 119
BAUDCON
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 333
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
88
RCREG EUSART Receive Data Register 326*
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 332
SPBRGL BRG<7:0> 334
SPBRGH BRG<15:8> 334
TRISC TRISC7 TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 133
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 331
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)