Datasheet

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 31
PIC16(L)F1782/3
Bank 4
20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 1111 1111
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111
20Fh
— Unimplemented — —
210h WPUE
— — — — WPUE3 — — — ---- 1--- ---- 1---
211h SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
212h SSPADD
ADD<7:0>
0000 0000 0000 0000
213h SSPMSK
MSK<7:0>
1111 1111 1111 1111
214h SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 0000 0000
215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
—
21Fh
— Unimplemented — —
Bank 5
28Ch ODCONA Open Drain Control for PORTA 0000 0000 0000 0000
28Dh ODCONB Open Drain Control for PORTB 0000 0000 0000 0000
28Eh ODCONC Open Drain Control for PORTC 0000 0000 0000 0000
28Fh
— Unimplemented — —
290h
— Unimplemented — —
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000
294h
—
297h
— Unimplemented — —
298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
29Ah CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 0000 0000 0000 0000
29Bh
—
29Fh
— Unimplemented — —
Bank 6
30Ch SLRCONA Slew Rate Control for PORTA 0000 0000 0000 0000
30Dh SLRCONB Slew Rate Control for PORTB 0000 0000 0000 0000
30Eh SLRCONC Slew Rate Control for PORTC 0000 0000 0000 0000
30Fh
—
31Fh
— Unimplemented — —
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: Unimplemented, read as ‘1’.