Datasheet

PIC16(L)F1782/3
DS41579D-page 30 Preliminary  2011-2012 Microchip Technology Inc.
Bank 2
10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu
10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu
10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu
10Fh
— Unimplemented — —
110h
— Unimplemented — —
111h
CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100
112h
CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000
113h
CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 0000 0100 0000 0100
114h
CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000
115h
CMOUT — — — — — MC3OUT MC2OUT MC1OUT ---- -000 ---- -000
116h BORCON SBOREN BORFS
— — — — — BORRDY 1x-- ---q uu-- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0 DACEN
--- DACOE1 DACOE2 DACPSS<1:0> --- DACNSS 0-00 00-0 0-00 00-0
119h DACCON1 DACR<7:0> 0000 0000 0000 0000
11Ah
to
11Ch
— Unimplemented — —
11Dh APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 0000 0000 0000 0000
11Eh
CM3CON0 C3ON C3OUT C3OE C3POL C3ZLF C3SP C3HYS C3SYNC 0000 0100 0000 0100
11Fh
CM3CON1 C3INTP C3INTN C3PCH<2:0> C3NCH<2:0> 0000 0000 0000 0000
Bank 3
18Ch
ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1-11 1111 1-11 1111
18Dh ANSELB
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111
18Eh
to
190h
— Unimplemented — —
191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000
192h EEADRH
—
(2)
EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000
193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h EEDATH
— — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM / Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON
— — — — — —VREGPMReserved ---- --01 ---- --01
198h
— Unimplemented — —
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRG BRG<7:0> 0000 0000 0000 0000
19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL
— SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: Unimplemented, read as ‘1’.