Datasheet

PIC16(L)F1782/3
DS41579D-page 266 Preliminary  2011-2012 Microchip Technology Inc.
25.4 Register Definitions: CCP Control
REGISTER 25-1: CCPxCON: CCPx CONTROL REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
R/W-0/0
— — DCxB<1:0> CCPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM<3:0>: CCPx Mode Select bits
11xx =PWM mode
1011 = Compare mode: Auto-conversion Trigger (sets CCPxIF bit (CCP2), starts ADC conversion if
ADC module is enabled)
(1)
1010 = Compare mode: generate software interrupt only
1001 = Compare mode: clear output on compare match (set CCPxIF)
1000 = Compare mode: set output on compare match (set CCPxIF)
0111 = Capture mode: every 16th rising edge
0110 = Capture mode: every 4th rising edge
0101 = Capture mode: every rising edge
0100 = Capture mode: every falling edge
0011 =Reserved
0010 = Compare mode: toggle output on match
0001 = Reserved
0000 = Capture/Compare/PWM off (resets CCPx module)