Datasheet

PIC16(L)F1782/3
DS41579D-page 264 Preliminary  2011-2012 Microchip Technology Inc.
EQUATION 25-2: PULSE WIDTH
EQUATION 25-3: DUTY CYCLE RATIO
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (F
OSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 25-4).
25.3.6 PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 25-4.
EQUATION 25-4: PWM RESOLUTION
TABLE 25-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F
OSC = 20 MHz)
TABLE 25-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F
OSC = 8 MHz)
Pulse Width CCPRxL:CCPxCON<5:4>  =
TOSC  (TMR2 Prescale Value)
Duty Cycle Ratio
CCPRxL:CCPxCON<5:4>
4PR2 1+
-----------------------------------------------------------------------=
Note: If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
Resolution
4PR2 1+log
2log
------------------------------------------ bits=
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6
PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5